Chemical-mechanical polishing (CMP) process for shallow trench isolation

A method of forming shallow trench isolations in the fabrication of an integrated circuit device comprising:

• growing a pad oxide layer overlying a silicon semiconductor substrate;
• depositing a polysilicon layer overlying said pad oxide layer;
• depositing a nitride layer overlying said polysilicon layer;
• etching trenches through said nitride layer, said polysilicon layer, and said pad oxide layer into said silicon semiconductor substrate;
• filling said trenches with an oxide layer wherein said oxide layer extends above a top surface of said nitride layer;
• depositing a silicon oxynitride layer overlying said oxide layer;
• first polishing away said silicon oxynitride layer and said oxide layer using a first slurry having high selectivity of oxide to nitride;
• second polishing away said oxide layer using a second slurry having a low selectivity of oxide to nitride and having low-defect properties;
• removing said nitride layer;
• and
• thereafter third polishing away said oxide layer using a third slurry having a high selectivity of oxide to polysilicon to complete formation of said shallow trench isolations in said fabrication of said integrated circuit device.