Electropolishing metal layers on wafers having trenches or vias with dummy structures
AssigneeACM Research, Inc.
InventorsHui Wang, Peihaur Yih
Life of this patent
Estimating the term…
Abstract
In electropolishing a metal layer on a semiconductor wafer, a dielectric layer is formed on the semiconductor wafer. The dielectric layer is formed with a recessed area and a non-recessed area. A plurality of dummy structures are formed within the recessed areas where the dummy structures are inactive areas configured to increase the planarity of a metal layer subsequently formed on the dielectric layer. A metal layer is then formed to fill the recessed area and cover the non-recessed area and the plurality of dummy structures. The metal layer is then electropolished to expose the non-recessed area.
Claims82
A method of electropolishing a metal layer on a semiconductor wafer comprising:
- forming a dielectric layer on the semiconductor wafer,
- wherein the dielectric layer is formed with a recessed area and a non-recessed area;
- forming a plurality of dummy structures within the recessed area,
- wherein the dummy structures are inactive areas configured to increase the planarity of a metal layer subsequently formed on the dielectric layer;
- forming a metal layer to fill the recessed area and cover the non-recessed area and the plurality of dummy structures;
- and
- electropolishing the metal layer to expose the non-recessed area.
A method of electropolishing a metal layer on a semiconductor wafer comprising:
- forming a dielectric layer on the semiconductor wafer,
- wherein the dielectric layer is formed with a recessed area and a non-recessed area;
- forming a plurality of dummy structures within the recessed area,
- wherein the plurality of dummy structures are inactive areas configured to increase the planarity of a metal layer subsequently formed on the dielectric layer;
- forming a barrier layer to cover the recessed area, the non-recessed area, and the plurality of dummy structures;
- forming a metal layer to fill the recessed area and cover the non-recessed area and the plurality of dummy structures;
- electropolishing the metal layer to expose the barrier layer deposited on the non-recessed area;
- removing the exposed barrier layer at a first rate;
- and
- removing the non-recessed area of the dielectric layer at a second rate.
A method of electropolishing a metal layer on a semiconductor wafer comprising:
- forming a dielectric layer on the semiconductor wafer,
- wherein the dielectric layer is formed with a recessed area and a non-recessed area;
- forming at least one dummy structure within the recessed area;
- forming a metal layer to cover the dummy structure and the non-recessed area and fill the recessed area;
- and
- overpolishing the metal layer from the recessed and non-recessed areas to expose the non-recessed area,
- wherein the overpolishing allows the non-recessed area to protrude past a surface of the metal layer in the recessed area.
A method of electropolishing a metal layer on a semiconductor wafer comprising:
- forming a dielectric layer on the semiconductor wafer,
- wherein the layer is formed with a recessed area, a non-recessed area, and a plurality of dummy structures disposed within the recessed area,
- wherein the dummy structures are inactive areas configured to increase the planarity of a metal layer subsequently formed on the layer;
- forming a metal layer to fill the recessed area and cover the non-recessed area and the dummy structures;
- and
- electropolishing the metal layer to expose the non-recessed area.
Dependencies are inferred from the claim text.