Metal gate double diffusion MOSFET with improved switching speed and reduced gate tunnel leakage

A method of fabricating a gate of a semiconductor device comprising:

• a) patterning a layer of silicon nitride on a silicon substrate;
• b) dosing the silicon substrate with a dopant to form a source region self-aligned to the silicon nitride;
• c) thermally treating the silicon substrate to diffuse a portion of the dopant laterally to form a diffused source region, a portion of the diffused source region underlying a portion of the layer of silicon nitride;
• then
• d) forming a silicon oxide layer on the substrate;
• e) planarizing the silicon oxide layer with the silicon nitride layer using a chemical-mechanical polishing technique to expose the silicon nitride layer;
• f) stripping the silicon nitride layer from the silicon substrate to form a gate region;
• g) forming a gate dielectric layer on the substrate in the gate region;
• h) sputtering aluminum-silicon-copper alloy to form a metal gate layer on at least the gate dielectric layer wherein a portion of the metal gate layer fills a volume previously filled by the silicon nitride;
• and
• i) planarizing the metal gate layer with the silicon oxide layer using a chemical-mechanical polishing technique.

A method comprising:

• a) forming a sacrificial gate structure of a device on a substrate, the gate structure having a first gate sacrificial gate portion and a second sacrificial gate portion, the first gate portion being separated from the second gate portion by a first window region;
• b) depositing a photoresist layer over the gate structure and the first window region;
• c) opening a second window region in the photoresist layer within the first window region between the first gate portion and the second gate portion;
• d) implanting a dose through the second window region into the substrate to form a heavily doped body;
• e) removing the photoresist layer after d);
• f) removing the sacrificial gate structure from the substrate;
• and
• g) forming a gate layer wherein at least a portion of the gate layer occupies a volume previously occupied by the sacrificial gate structure.