Method of forming a composite spacer to eliminate polysilicon stringers between elements in a pseudo SRAM cell

A method of forming buried stack capacitor structures on a semiconductor substrate, featuring a dry-wet etch procedure to define silicon oxide spacer components of composite insulator spacers, located on the sides of said buried stack capacitor structures, comprising the steps of:

• forming shallow trench shapes in a composite insulator layer, and in a top portion of said semiconductor substrate;
• depositing a first silicon oxide layer completely filling said shallow trench shapes;
• removing portions of said first silicon oxide layer from the top surface of said composite insulator layer resulting in silicon oxide filled, shallow trench isolation (STI) regions located in said top portions of said semiconductor substrate;
• performing a first anisotropic reactive ion etch (RIE) procedure to form recesses in top portions of first sections of said STI regions, while second sections of said STI regions remain unetched;
• depositing a first polysilicon layer;
• performing a first ion implantation procedure to place ions into said first polysilicon layer creating a first doped polysilicon layer;
• forming photoresist plug structures on portions of said first doped polysilicon layer located in said recesses in said top portions of first sections of said STI region;
• removing portions of said first doped polysilicon layer not protected by said photoresist plug structures, resulting in definition of polysilicon storage node structures in said recesses located in said top portions of said first sections of said STI regions;
• removing said composite insulator layer from portions of the top surface of said semiconductor substrate not occupied by said STI regions;
• forming a capacitor dielectric layer on said polysilicon storage node structures;
• depositing a second polysilicon layer;
• performing a second ion implantation procedure to place ions into said second polysilicon layer creating a second doped polysilicon layer;
• depositing an insulator stop layer on said second doped polysilicon layer;
• performing a second anisotropic RIE procedure to create insulator stop shapes, polysilicon top plate structures, and capacitor dielectric shapes, on underlying polysilicon storage node structure, resulting in said buried stack capacitor structures located on said first sections of said STI regions, each comprised with an overlying insulator stop layer shape, a polysilicon top plate structure, a capacitor dielectric layer, and with a polysilicon storage node structure, and with said second sections of said STI regions not covered by said buried stack capacitor structures;
• depositing a silicon nitride layer;
• performing a third anisotropic RIE procedure forming silicon nitride spacers on the sides of said buried stack capacitor structures;
• depositing a second silicon oxide layer;
• performing a fourth anisotropic RIE procedure removing a top portion of said second silicon oxide layer resulting in partially defined, initial silicon oxide spacers, and resulting in bottom portions of said second silicon oxide layer remaining on said second sections of said STI regions, and on areas of said semiconductor substrate located between said buried stack capacitor structures;
• and
• performing a wet etch procedure to remove bottom portions of said second silicon oxide layer defining final silicon oxide spacers and resulting in said composite insulator spacers on sides of said buried stack capacitor structures, wherein said composite insulator spacers are comprised of final silicon oxide spacers on said silicon nitride spacers, and with said wet etch procedure establishing a smooth topography on said second sections of STI regions, and establishing a gradual slope at the interface of a composite insulator spacer and a second section of said STI region.