Method of manufacturing gate driver with level shift circuit

A method for forming a gate driver configured to drive a power semiconductor device, comprising:

• providing a substrate having an upper surface;
• forming a first circuit on the substrate, wherein the forming-a-first-circuit includes
• forming a first conductive region on a portion of the upper surface of the substrate,
• forming a first dielectric layer overlying the first conductive region,
• forming a first conductive layer provided over the first conductive layer and at least a portion of the first dielectric layer, the first conductive layer configured to be a resistor,
• forming a first metal structure electrically coupled to the first conductive region and the first conductive layer, and
• forming a second metal structure electrically coupled to the first conductive layer, wherein the first conductive region, the first conductive layer, and the at least portion of the first dielectric layer together form a first capacitor, and the first conductive region, the second metal structure, and a portion of the first dielectric layer form a second capacitor;
• and
• forming a second circuit on the substrate, wherein the forming-a-secondcircuit includes:
• forming a second conductive region on a portion of the upper surface of the substrate,
• forming a second dielectric layer overlying the second conductive region,
• forming a second conductive layer provided over the second conductive region and at least a portion of the second dielectric layer, the second conductive layer configured to be a resistor,
• forming a third metal structure electrically coupled to the second conductive region and the second conductive layer, and
• forming a fourth metal structure electrically coupled to the second conductive layer, wherein the second conductive region, the second conductive layer, and the at least portion of the second dielectric layer together form a third capacitor, and the second conductive region, the fourth metal structure, and a portion of the second dielectric layer form a fourth capacitor.

A method for forming a gate driver configured to drive a power semiconductor device, comprising:

• providing a substrate having an upper surface;
• forming a conductive region on a portion of the upper surface of the substrate;
• forming a dielectric layer overlying the conductive region;
• forming a first conductive layer provided over the conductive region and at least a portion of the dielectric layer;
• patterning the first conductive layer to provide the first conductive layer with a given resistance value;
• forming a second conductive layer over the dielectric layer and electrically coupled to the conductive region and first conductive layer;
• and
• patterning the second conductive layer to provide an input node that is coupled to a first portion of the resistor and an output node that is coupled to a second portion of the resistor,
• wherein the input node is configured to receive a control signal from a control signal generator and the output node is configured to receive the control signal from the input node via the resistor,
• wherein the conductive region, the first conductive layer, and the at least portion of the dielectric layer together form a first capacitor.