Instruction reducing predicate copy
AssigneeIntel Corporation
InventorWilliam Y. Chen
Life of this patent
Estimating the term…
Abstract
When compiling software for a processor that supports predication, an alerting instruction can be inserted to alert a global register allocator to map particular virtual predicates into the same physical registers. Redundant predicate generating instructions are removed from the resulting program. The alerting instruction can be a predicate copy pseudo-opcode. When the register allocator maps the virtual predicates into the same physical register, the predicate copy pseudo-opcode is removed. When the register allocator does not map the virtual predicates to the same physical register, the predicate copy pseudo-opcode is replaced by an instruction that will perform a predicate copy.
Claims36
A computer-implemented method for reducing the number of predicate generating instructions in software comprising:
- locating two non-equivalent blocks that are path-equivalent;
- removing a predicate generating instruction from a block preceding the two non-equivalent blocks, the predicate generating instruction being configured to generate a predicate that guards execution of one of the two non-equivalent blocks.
An article comprising a machine readable medium including instructions for a method of reducing the number of predicate generating instructions in machine code, the method comprising:
- locating two non-equivalent blocks that are path-equivalent;
- removing a predicate generating instruction from a block preceding the two non-equivalent blocks, the predicate generating instruction being configured to generate a predicate that guards execution of one of the two non-equivalent blocks.
A computer implemented method of mapping predicate names to predicate registers comprising:
- identifying a first live range of a first predicate name;
- identifying a second live range of a second predicate name;
- and
- when the first live range does not overlap with the second live range, and an alerting instruction exists between the first live range and the second live range, assigning the first predicate name and the second predicate name to a single predicate register.
A computer-implemented method of mapping predicate names to predicate registers comprising:
- identifying a first live range of a first predicate name;
- identifying a second live range of a second predicate name;
- when the first live range does not overlap with the second live range, and an alerting instruction exists between the first live range and the second live range, assigning the first predicate name to a first predicate register and the second predicate name to a second predicate register;
- and
- at the location of the alerting instruction, inserting a predicate generating instruction that assigns the value of the first predicate register to the second predicate register.
A computer-implemented method of removing predicate generating instructions from software compiled to run on a processor that supports predication, the method comprising:
- identifying a first block having a plurality of predicate generating instructions, including a first predicate generating instruction and a second predicate generating instruction, wherein the first predicate generating instruction is configured to alter a first predicate register and the second predicate generating instruction is configured to alter a second predicate register;
- searching for two path-equivalent blocks each guarded by at least one of the first predicate register and the second predicate register;
- and
- removing at least one of the plurality of predicate generating instructions from the first block.
An article comprising a machine readable medium including instructions for a method of removing predicate generating instructions from software compiled to run on a processor that supports predication, the method comprising:
- identifying a first block having a plurality of predicate generating instructions, including a first predicate generating instruction and a second predicate generating instruction, wherein the first predicate generating instruction is configured to alter a first predicate register and the second predicate generating instruction is configured to alter a second predicate register;
- searching for two path-equivalent blocks each guarded by at least one of the first predicate register and the second predicate register;
- and
- removing at least one of the plurality of predicate generating instructions from the first block.
A computer-implemented method of mapping virtual predicate names to physical predicate registers comprising:
- identifying two non-equivalent blocks that are path-equivalent with respect to each other;
- assigning different virtual names to the two non-equivalent blocks, the different virtual names having live ranges that do not overlap;
- and
- assigning the different virtual names to a single predicate register.
An article comprising a machine readable medium including instructions for a method of mapping virtual predicate names to physical predicate registers, the method comprising:
- identifying two non-equivalent blocks that are path-equivalent with respect to each other;
- assigning different virtual names to the two non-equivalent blocks, the different virtual names having live ranges that do not overlap;
- and
- assigning the different virtual names to a single predicate register.
A system comprising:
- a random access memory to store at least a part of a number of instructions having a number of predicate generating instructions;
- and
- a processor to compile the number of instructions wherein one of the predicate generating instructions is removed from a block of the number of instructions that precedes two non-equivalent blocks of the number of instructions that are path-equivalent, the one of the predicate generating instructions to generate a predicate that guards execution of one of the two non-equivalent blocks.
A machine readable medium that provides instructions, which when executed by a machine, cause the machine to perform operations comprising:
- compiling a number of instructions that includes a number of predicate generating instructions, wherein compiling comprises locating two non-equivalent blocks that are path-equivalent and wherein compiling comprises removing a predicate generating instruction from a block preceding the two non-equivalent blocks, the predicate generating instruction to generate a predicate that guards execution of one of the two non-equivalent blocks;
- and
- performing global register allocation subsequent to the compiling of the number of instructions, wherein performing global register allocation comprises assigning a single physical predicate register to guard execution of the two non-equivalent blocks.
Dependencies are inferred from the claim text.