US 6,637,014 B2 · Crosstalk mitigation method and system

Abstract

A method and system of crosstalk mitigation in integrated circuits employs delay change curves (DCCs) and uses targeted transistor sizing and/or buffer insertion. Based on a timing graph, a longest path capable of being shortened may be shortened by victim strengthening or aggressor weakening when a setup requirement time violation occurs and the path is capable of being shortened. The process is repeated based on an updated timing graph until the longest path is not capable of being further shortened, or there is no setup requirement time violation. Additionally, the path may be lengthened where a hold requirement time violation has occurred and the path is capable of being lengthened, by victim strengthening or aggressor weakening, until the path cannot be further lengthened or there is no hold requirement time violation. Victim strengthening is performed by altering the critical path, and aggressor weakening is performed by altering the non-critical path.

Claims30

Dependent claims

A method of mitigating crosstalk, comprising:

(a) generating a timing graph based on static timing analysis and paths having input gates coupled by timing arcs;
(b) determining a longest path in said timing graph that can be shortened;
(c) comparing a length of a selected path to a clock period and setup time;
(d) shortening said selected path by strengthening a victim or weakening an aggressor on said selected when a setup time violation exists for said selected path and said selected path can be shortened;
(e) recalculating said timing graph in accordance with (d);
and
(f) performing (c) through (e) until no setup time violation exists for said selected path, or said selected path cannot be further shortened.

4 more elements

Dependencies are inferred from the claim text.

Crosstalk mitigation method and system

Life of this patent

Crosstalk mitigation method and system

Life of this patent

Abstract

Claims30