Method and system for identifying FETs implemented in a predefined logic equation
AssigneeHewlett-Packard Development Company, L.P.
InventorsS. Brandon Keller, Gregory Dennis Rogers
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Abstract
A method for identifying FETs implemented in a predefined logic equation defined by at least one signal name from a netlist having output nodes, supply voltages with their opposite supply voltages, and FETs with their connectivity, that includes the steps of selecting an output node from the netlist, preparing the predefined logic equation for searching FETs in the netlist, and identifying FETs from the netlist that are implemented in the prepared predefined logic equation.
Claims20
A method for identifying FETs implemented in a predefined logic equation defined by at least one signal name from a netlist having output nodes, FETs and their connections, said method comprising the steps of:
- selecting an output node from the netlist;
- preparing the predefined logic equation for searching FETs in the netlist;
- and,
- identifying FETs from the netlist that are implemented in the prepared predefined logic equation;
- wherein said preparing step further comprises:
- searching for a N-tree on the selected output node from the netlist that matches the prepared predefined logic equation;
- determining whether the predefined equation is inverted;
- finding an inverter on the output node when the predefined equation is not inverted;
- determining whether an inverter is found;
- simplifying the predefined equation when an inverter is found;
- and,
- aborting the process when an inverter is not found.
A method for identifying FETs implemented in a predefined logic equation defined by at least one signal name from a netlist having output nodes, FETs and their connections, said method comprising the steps of:
- selecting an output node from the netlist;
- preparing the predefined logic equation for searching FETs in the netlist;
- and,
- identifying FETs from the netlist that are implemented in the prepared predefined logic equation;
- wherein said preparing stem further comprises:
- searching for a P-tree on the selected output node from the netlist that matches the prepared predefined logic equation;
- determining whether the predefined logic equation is inverted;
- simplifying the inverted predefined logic equation;
- and,
- inverting each signal name in the inverted predefined logic equation.
A method for identifying FETs implemented in a predefined logic equation defined by at least one signal name from a netlist having output nodes, FETs and their connections, said method comprising the steps of:
- selecting an output node from the netlist;
- preparing the predefined logic equation for searching FETs in the netlist;
- and,
- identifying FETs from the netlist that are implemented in the prepared predefined logic equation;
- wherein said identifying step further comprises:
- identifying a channel connected FET on the output node;
- determining whether the gate signal of the identified FET is in the predefined logic equation;
- creating a hash table key for the gate signal of the identified FET when the gate signal is in the predefined logic equation;
- and,
- adding said identified FET to a list associated with the hash table key.
A computer system for identifying FETs implemented in a predefined logic equation from a netlist having output nodes, FETs and their connections, comprising:
- a storage medium;
- a processor for executing a program stored on the storage medium for identifying FETs implemented in a predefined logic equation from a netlist having output nodes, supply voltages with their opposite supply voltages, and FETs with their connectivity, the program comprising a set of instructions for:
- selecting an output node;
- preparing the predefined logic equation for searching FETs in the netlist;
- identifying FETs from the netlist that are implemented in the prepared predefined logic equation;
- and,
- outputting the identified FETs:
- wherein said preparing step further comprises:
- searching for a N-tree on the selected output node from the netlist that matches the prepared predefined logic equation;
- determining whether the predefined equation is inverted;
- finding an inverter on the output node when the predefined equation is not inverted;
- determining whether an inverter is found;
- simplifying the predefined equation when an inverter is found;
- and,
- aborting the process when an inverter is not found.
A computer program product comprising a computer usable medium having computer readable program codes embodied in the medium that when executed causes a computer to:
- selecting an output node;
- prepare a predefined logic equation for searching FETs in a netlist;
- identify FETs from the netlist that are implemented in the prepared predefined logic equation;
- and,
- output the identified FETs;
- wherein said preparing step further comprises:
- searching for a N-tree on the selected output node from the netlist that matches the prepared predefined logic equation;
- determining whether the predefined equation is inverted:
- finding an inverter on the output node when the predefined equation is not inverted;
- determining whether an inverter is found;
- simplifying the predefined equation when an inverter is found;
- and,
- aborting the process when an inverter is not found.
A computer system for identifying FETs implemented in a predefined logic equation from a netlist having output nodes, FETs and their connections, comprising:
- a storage medium;
- a processor for executing a program stored on the storage medium for identifying FETs implemented in a predefined logic equation from a netlist having output nodes, supply voltages with their opposite supply voltages, and FETs with their connectivity, the program comprising a set of instructions for:
- selecting an output node;
- preparing the predefined logic equation for searching FETs in the netlist;
- identifying FETs from the netlist that are implemented in the prepared predefined logic equation;
- and,
- outputting the identified FETs;
- wherein said identifying step further comprises:
- identifying a channel connected FET on the output node;
- determining whether the gate signal of the identified FET is in the predefined logic equation;
- creating a hash table key for the gate signal of the identified FET when the gate signal is in the predefined logic equation;
- and,
- adding said identified FET to a list associated with the hash table key.
A computer program product comprising a computer usable medium having computer readable program codes embodied in the medium that when executed causes a computer to:
- selecting an output node;
- prepare a predefined logic equation for searching FETs in a netlist;
- identify FETs from the netlist that are implemented in the prepared predefined logic equation;
- and,
- output the identified FETs;
- wherein said preparing stem further comprises:
- searching for a P-tree on the selected output node from the netlist that matches the prepared predefined logic equation;
- determining whether the predefined logic equation is inverted;
- simplifying the inverted predefined logic equation;
- and,
- inverting each signal name in the inverted predefined logic equation.
A computer program product comprising a computer usable medium having computer readable program codes embodied in the medium that when executed causes a computer to:
- selecting an output node;
- prepare a predefined logic equation for searching FETs in a netlist;
- identify FETs from the netlist that are implemented in the prepared predefined logic equation;
- and,
- output the identified FETs;
- wherein said identifying step further comprises:
- identifying a channel connected FET on the output node;
- determining whether the gate signal of the identified FET is in the predefined logic equation;
- creating a hash table key for the gate signal of the identified FET when the gate signal is in the predefined logic equation;
- and,
- adding said identified FET to a list associated with the hash table key.
Dependencies are inferred from the claim text.