Decoder for error correcting block codes
AssigneeMaxtor Corporation
InventorsLih-Jyh Weng, Ba-Zhong Shen, Shih Mo, Chung Chang
Life of this patent
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Abstract
A decoder for decoding block error correction codes is described. The decoder includes a first search circuit to find roots of an error location polynomial corresponding to an error location and a second search circuit to find roots of an error location polynomial corresponding to an error location. A multiplexer is fed by the first search circuit and the second search circuit to produce an error location from the error location polynomial.
Claims60
A decoder for decoding block error correction codes comprises:
- a first search circuit that evaluates an error location polynomial to find a root corresponding to an error location;
- a second search circuit that evaluates the error location polynomial to find a root corresponding to an error location;
- and
- a multiplexer fed by the first search circuit and the second search circuit to produce an error location from a said root.
A decoder for decoding block codes comprises:
- a parallel error location polynomial search circuit comprising:
- a first search circuit that evaluates an error location polynomial to find a root that corresponds to an error location, said first search circuit further comprising:
- a first modulo adder circuit that adds odd terms of the error location polynomial to produce a derivative of the error location polynomial;
- a second search circuit that evaluates the error location polynomial to find a root that corresponds to an error location, said second search circuit further comprising:
- a second modulo adder circuit that adds odd terms of the error location polynomial to produce a derivative of the error location polynomial;
- a first multiplexer fed by the first search circuit and the second search circuit to produce an error location from a said root;
- a second multiplexer fed by the error locator polynomial derivatives from the first and second modulo adders;
- an error evaluation circuit that produces an error evaluator polynomial;
- and
- a logic circuit including a divider circuit to divide the error evaluator polynomial by the output from the second multiplexer.
A method of decoding an error correcting block code comprises:
- evaluating an error location polynomial produced from an error location polynomial generation circuit by applying the error location polynomial to a parallel root search circuit that searches for roots of the error location polynomial in a parallel manner.
A decoder to decode block error correction codes, comprising:
- parallel search circuits that evaluate a single error location polynomial to find roots that correspond to error locations of data from a storage medium;
- wherein a first root σ(α−(2j)) of the single error location polynomial comprises:
- σ(α−(2j))=regk(0)(j)+regk−1(0)(j)+ . . . +reg1(0)(j)+reg0(0)(j);
- and
- wherein a second root σ(α−(2j+1)) of the single error location polynomial comprises:
- σ(α−(2j+1))=regk(1)(j)+regk−1(1)(j)+ . . . +reg1(1)(j)+reg0(1)(j)
- with values for reg comprising data register values.
A decoder comprising:
- a generator circuit that generates an error location polynomial from error correcting code symbols that correspond to data on a storage medium;
- parallel search circuits that search for roots of the error location polynomial;
- and
- an evaluator circuit that evaluates errors in the error correcting code symbols at locations that correspond to the roots.
A method comprising:
- generating an error location polynomial from error correcting code symbols that correspond to data on a storage medium;
- searching for roots of the error location polynomial via parallel search circuits;
- and
- evaluating errors in the error correcting code symbols at locations that correspond to the roots.
A method comprising:
- searching for roots of a single error location polynomial using parallel search circuits.
A decoder for decoding block error correction codes, comprising:
- means for evaluating a single error location polynomial to find a first root corresponding to an error location;
- means for evaluating the single error location polynomial to find a second root corresponding to an error location;
- and
- means for producing an error location of the root based on the first and second roots.
A decoder comprising:
- means for generating a single error location polynomial from error correcting code symbols that correspond to data on a storage medium;
- means for searching for roots of the single error location polynomial via parallel search circuits;
- and
- means for evaluating errors in the error correcting code symbols at locations that correspond to the roots.
Dependencies are inferred from the claim text.