US 6,636,999 B1Granted

Clock adjusting method and circuit device

AssigneeFujitsu Limited

InventorJun Yamada

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Abstract

A clock adjusting method adjusts a first clock supplied to a first flip-flop which is coupled to an output of a first circuit and a second clock supplied to a second flip-flop which is coupled to an input of a second circuit, where the first and second flip-flops are coupled via a transmission path. The clock adjusting method includes the steps of (a) transmitting data from the first flip-flop to the second flip-flop via the transmission path while varying delay quantities of the first and second clocks, (b) obtaining a combination of the delay quantities of the first and second clocks with which the data is correctly transmitted from the first flip-flop to the second flip-flop, and (c) adjusting the delay quantity of at least one of the first and second clocks based on the combination so as to synchronize operations of the first and second flip-flops.

Claims8

Dependent claims

A clock adjusting method for adjusting a first clock supplied to an output flip-flop and a second clock supplied to an input flip-flop in a circuit device so as to synchronize operations of the output flip-flop and the input flip-flop, said output flip-flop holding a state of an output signal of a signal processing circuit, said input flip-flop holding a state of a signal output from the output flip-flop, said first clock being output from a first adjusting circuit which delays a clock from a clock oscillator, said second clock being output from a second adjusting circuit which delays the clock from the clock oscillator, said clock adjusting method comprising:

an output state detecting procedure, detecting output signal states of the output flip-flop and the input flip-flop by repeating an operation of controlling the clock oscillator to supply the first clock to the output flip-flop and the second clock to the input flip-flop while varying delay quantities of the first and second adjusting circuits;
and
a delay quantity setting procedure, detecting a combination of delay quantities of the first and second adjusting circuits with which the output signal state of the output flip-flop is correctly transmitted to the input flip-flop, based on the output signal states of the output flip-flop and the input flip-flop detected by said output state detecting procedure, and setting the delay quantities of the first and second adjusting circuits depending on the detected combination.

Dependencies are inferred from the claim text.