Semiconductor memory device and parallel bit test method thereof

Abstract

A semiconductor memory device and a parallel bit test method thereof comprises a memory cell array having a plurality of memory cells, an address generator for accessing memory cells of the memory cell array in response to externally applied addresses; a test mode setting register for storing an externally applied test mode setting command; a test pattern data register for storing test pattern data applied from the test mode setting register and for outputting test pattern data at the time of performing a read command; and a comparator for comparing data read from the memory cells of the memory cell array with data of corresponding bits of test pattern data output from the test pattern data register and for generating test result data. Accordingly, the device is adapted for correctly detecting and distinguishing defective memory cells, and is amenable to performing bit tests using various non-uniform test pattern data.

Dependencies are inferred from the claim text.