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US 6,636,996 B2Granted
Method and apparatus for testing pipelined dynamic logic
AssigneeInternational Business Machines Corporation
InventorKevin J. Nowka
Life of this patent
Estimating the term…
Abstract
A method and apparatus for testing pipelined dynamic logic makes it possible to set and retrieve values from dynamic logic pipelines that have no internal latches. A modification to the pipeline circuits and clocking circuitry enable scanning logic to set and retrieve values from the pipelined circuits.
Claims20
An integrated circuit comprising:
- a tester interface;
- a dynamic logic pipeline;
- an input scan latch coupled to said tester interface configured to hold a value loadable into a dynamic logic gate within said dynamic logic pipeline;
- and
- a scan ladder coupled to an evaluation node of said dynamic logic gate and further coupled to a load clock of said tester interface, such that said scan ladder may discharge said evaluation node in conformity with said value.
2 more elements
A dynamic logic gate, comprising:
- a preset device coupled to an evaluation node of said dynamic logic gate for charging said evaluation node to a preset state;
- a logic input ladder coupled to said evaluation node for discharging said evaluation node in conformity with a state of logic inputs;
- and
- a scan ladder coupled to said evaluation node, said scan ladder having an input for coupling a load clock for testing said dynamic logic gate.
1 more element
A method for testing pipelined dynamic logic within an integrated circuit, said method comprising the steps of:
- loading a value into a scan latch from a scan chain;
- presetting an evaluation node within said dynamic logic;
- determining whether or not said integrated circuit is transitioning from scan mode to functional mode;
- and
- in response to determining that said integrated circuit is transitioning from scan mode to functional mode, discharging said evaluation node in conformity with said value.
2 more elements
Dependencies are inferred from the claim text.