Method of automatic latch insertion for testing application specific integrated circuits

A method of testing a digital logic circuit comprising:

• providing a logic circuit having a plurality of interconnected circuits each having an input and an output;
• determining a gate level representation of the logic circuit including test nets for determining faults in the circuit;
• identifying a portion of the nets which are most difficult to test by overall test time impact, including nets having longest test times which are most difficult to control and which are most difficult to observe, and further including tracing logic network of the logic circuit and determining for each net a score of:
• i) distance in logic levels from a source latch;
• ii) distance in logic levels from a destination latch;
• iii) logic cone size that generates the net;
• and iv) number of latches fed by the cone driven by the net;
• inserting into the logic circuit control latches for nets which are determined to be most difficult to control and which have qualitative scores which differ most from predetermined scores;
• inserting into the logic circuit observation latches for nets which are determined to be most difficult to observe and which have qualitative scores which differ most from predetermined scores;
• using the inserted control latches and observation latches, first testing the nets which are determined to be most difficult to control and nets which are hardest to observe and determining faults in the circuit, wherein testing is completed in a time faster than if the nets were tested without the control latches and the observation latches.

A method of testing a digital logic circuit comprising:

• providing a logic circuit having a plurality of interconnected circuits each having an input and an output;
• determining a gate level representation of the logic circuit including test nets for determining faults in the circuit;
• identifying a portion of the nets which are most difficult to test by overall test time impact, including nets having longest test times which are most difficult to control and which are most difficult to observe, by using a test diagnosis tool to determine test patterns, determining faults covered by each test pattern, and for each net the number of vectors needed before the net was tested;
• inserting into the logic circuit control latches for nets which are determined to be most difficult to control, as either determined to be not testable or which have the most vectors applied before the net was tested;
• inserting into the logic circuit observation latches for nets which are determined to be most difficult to observe, as either determined to be not testable or which have the most vectors applied before the net was tested;
• using the inserted control latches and observation latches, first testing the nets which are determined to be most difficult to control and nets which are hardest to observe and determining faults in the circuit, wherein testing is completed in a time faster than if the nets were tested without the control latches and the observation latches.

A method of testing a digital logic circuit comprising:

• providing a logic circuit having a plurality of interconnected circuits each having an input and an output;
• determining a gate level representation of the logic circuit including test nets for determining faults in the circuit;
• identifying a portion of the nets which are most difficult to test by overall test time impact, including nets having longest test times which are most difficult to control and which are most difficult to observe;
• inserting into the logic circuit control latches for nets which are determined to be most difficult to control;
• breaking the logic cone that generates the nets into at least two pieces;
• inserting into the logic circuit of each piece of logic cone observation latches for nets which are determined to be most difficult to observe and, optionally, control latches for nets which are determined to be most difficult to control;
• using the inserted control latches and observation latches, first testing the nets which are determined to be most difficult to control and nets which are hardest to observe and determining faults in the circuit, wherein testing is completed in a time faster than if the nets were tested without the control latches and the observation latches.

A method of testing a digital logic circuit comprising:

• providing a logic circuit having a plurality of interconnected circuits each having an input and an output;
• determining a gate level representation of the logic circuit including test nets for determining faults in the circuit;
• identifying a portion of the nets which are most difficult to test by overall test time impact, including nets having longest test times which are most difficult to control and which are most difficult to observe;
• inserting into the logic circuit control latches for nets which are determined to be most difficult to control;
• inserting into the logic circuit observation latches for nets which are determined to be most difficult to observe;
• using the inserted control latches and observation latches, first testing the nets which are determined to be most difficult to control and nets which are hardest to observe, including calculating new design area and new timing slack for logic paths having the inserted control latches and observation latches, and determining faults in the circuit, wherein testing is completed in a time faster than if the nets were tested without the control latches and the observation latches.