Flexible method for satisfying complex system error handling requirements via error promotion/demotion

Error handling logic for a processor having a plurality of error types each of which is assigned to a signaling mechanism, comprising:

• a register storing a promotion/demotion value for at least one error;
• error detection logic;
• and
• error promotion/demotion logic receiving inputs from said register and said error detection logic and producing an output to one of said signaling mechanisms,
• wherein said register includes a value for enabling promotion of a first signaling mechanism to a second signaling mechanism, and
• wherein said promotion includes the processor correcting errors but generating the second signaling mechanism.

Error handling logic for a processor having a plurality of error types each of which is assigned to a signaling mechanism, comprising:

• a register storing a promotion/demotion value for at least one error;
• error detection logic;
• and
• error promotion/demotion logic receiving inputs from said register and said error detection logic and producing an output to one of said signaling mechanisms,
• wherein said register includes a value for enabling promotion of a first signaling mechanism to a second signaling mechanism, and
• wherein said promotion includes asserting an external pin.

Error handling logic for a processor having a plurality of error types each of which is assigned to a signaling mechanism, comprising:

• a register storing a promotion/demotion value for at least one error;
• error detection logic;
• and
• error promotion/demotion logic receiving inputs from said register and said error detection logic and producing an output to one of said signaling mechanisms,
• wherein said register includes a value for enabling promotion of a first signaling mechanism to a second signaling mechanism, and
• wherein said promotion includes the processor asserting an external pin and performing a reset operation.