Output and/or input coordinated processing array
AssigneeHyperchip Inc.
InventorRichard S. Norman
Life of this patent
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Abstract
A data processing system containing a monolithic network of cells with sufficient redundancy provided through direct logical replacement of defective cells by spare cells to allow a large monolithic array of cells without uncorrectable defects to be organized, where the cells have a variety of useful properties. The data processing system according to the present invention overcomes the chip-size limit and off-chip connection bottlenecks of chip-based architectures, the von Neumann bottleneck of uniprocessor architectures, the memory and I/O bottlenecks of parallel processing architectures, and the input bandwidth bottleneck of high-resolution displays, and supports integration of up to an entire massively parallel data processing system into a single monolithic entity.
Claims40
A data processing system on a single substrate, comprising:
- an array of cells, each cell including a processor, memory, direct output means, and means for coordinating a timing of output through the direct output means to permit the array of cells to serve as a phased array for focusing direct outputs on an external receiver.
A data processing system on a single substrate, comprising:
- an array of cells, each cell including a processor, memory, direct output means, and means for controlling a phase of output through the direct output means to permit the array of cells to serve as a phased array for direct outputs to an external receiver.
A data processing system on a single substrate, comprising:
- an array of cells, each cell including a processor, memory, direct input means for receiving data from an external transmitter, and means for coordinating a timing of output of the data to a data bus in common with other cells.
A method of focusing output from a network of cells having output means, comprising steps of:
- receiving at an input means of each cell an external reference signal from an external device on which the output is to be focused;
- noting a time at each cell when the external reference signal was received;
- sending an internal reference signal to cells in the network after the input is received by a controller for the network of cells, such that said internal reference signal is received by all the cells substantially simultaneously;
- noting a time difference at each cell between when the internal reference signal is received and the external reference signal was received;
- and
- at each cell, operating the output means after a delay directly proportional to the time difference to focus the output on the external device.
A method of coordinating the phase of outputs from a network of cells having output means, comprising steps of:
- receiving at an input means of each cell an external reference signal from an external device on which the output is to be focused;
- sending an internal reference signal to all cells in the network so that it is received substantially simultaneously by all cells;
- noting the phase of the input at each cell when the internal reference signal is received;
- at each, operating the output means with a phase shift directly proportional to the noted phase, and opposite in sign, so that the phases of the outputs are coordinated to focus the combined output on the external device.
A method of focusing input to a system comprising a network of cells having input means, the method comprising steps of:
- receiving at an input means of each cell an external reference signal from an external source;
- noting the time at each cell when the external reference signal was received;
- sending an internal reference signal to all cells in the network so that it is received at substantially the same time by all cells;
- receiving at an input means of each cell a data input from the external source;
- and
- at each cell, putting the data input on a common data bus after a delay that is directly proportional to a difference between the time that the external reference was received and the time that the internal reference was received, so that the data input signal from all cells is added together on the global data bus.
Dependencies are inferred from the claim text.