US 6,636,980 B1 · System for launching data on a bus by using first clock for alternately selecting data from two data streams and using second clock for launching data thereafter

Abstract

A bus interface apparatus and method are implemented. A pair of data streams is generated from the stream of data to be launched onto a data bus. Each stream is staged along a corresponding data path that includes a plurality of storage elements. Each path feeds an input of a multiplexer (MUX). The output of the MUX drives the bus, and the MUX selects a data value for launching onto the bus in response to a signal derived from an internal bus clock. The internal bus clock is also used to generate a bus clock that is output to the bus along with the data. The period of the bus clock may be a preselected multiple of the period of a processor clock. The data is staged along the two data streams in response to clocking signals derived from the processor clock. Each of the clocking signals is qualified by a corresponding hold signal, that, when asserted, holds the clocking signals in a predetermined state. The hold signals are generated in response to a plurality of control signals that are used to select the ratio of bus clock period to processor clock period. The bus interface may be asynchronously started in response to a signal from the startup logic in the central processing unit (CPU).

Claims24

Dependent claims

A bus interface apparatus comprising:

circuitry operable for receiving a first data stream for outputting on a bus and generating second and third data streams in response to said first data stream;
selection circuitry operable for alternatively selecting, in response to a select signal, from said second and third data streams a sequence of data values for outputting on said bus, wherein said select signal is generated in response to a first bus clock;
and
circuitry for outputting a second bus clock to said bus in response to said first bus clock, wherein a data valid interval of each value of said sequence of data values has a preselected relationship with respect to said second bus clock determined by said circuitry operable for generating said second and third data streams.

1 more element

A method of launching data on a bus comprising the steps of:

receiving a first data stream operable for launching on said data bus;
generating second and third data streams in response to said first data stream;
receiving a first bus clock and generating a select signal in response thereto;
alternately selecting from said second and third data streams a sequence of data values for launching on said bus in response to said select signal, wherein said step of generating second and third data streams comprises the steps of:
providing said first data stream to first and second pluralities of storage elements;
and
staging said first data stream through said first and second pluralities of storage elements in response to a plurality of clocking signals, outputs of said first and second pluralities of storage elements providing said second and third data streams;
and
generating a second bus clock to said bus in response to said first bus clock, wherein a data valid interval of each value of said sequence of data values has a preselected relationship with respect to said second bus clock determined by the step of generating said second and third data streams.

6 more elements

A data processing system comprising:

a memory coupled to a memory bus;
and
central processing unit (CPU), said CPU including a bus interface coupled to said memory bus, said bus interface comprising:
circuitry operable for receiving a first data stream for outputting on said memory bus and generating second and third data streams in response to said first data stream;
selection circuitry operable for alternatively selecting from said second and third data streams a sequence of data values for outputting on said bus, wherein said selection circuitry selects for outputting in response to a select signal, wherein said select signal is generated in response to a first bus clock;
and
circuitry for outputting a second bus clock to said memory bus in response to said first bus clock, a data valid interval of each value of said sequence of data values having a preselected relationship with respect to said second bus clock determined by said circuitry operable for generating said second and third data streams.

4 more elements

Dependencies are inferred from the claim text.

System for launching data on a bus by using first clock for alternately selecting data from two data streams and using second clock for launching data thereafter

Life of this patent

System for launching data on a bus by using first clock for alternately selecting data from two data streams and using second clock for launching data thereafter

Life of this patent

Abstract

Claims24