System for measuring phase error between two clocks by using a plurality of phase latches with different respective delays

A phase error measurement circuit comprising:

• a first clock signal input;
• a second clock signal input;
• means for delaying the first clock signal input by a plurality of phase lead measuring delays to produce a plurality of delayed first clock signal inputs;
• means for delaying the second clock signal input by a plurality of phase lag measuring delays to produce a plurality of delayed second clock signal inputs;
• phase lead measurement means for detecting whether the plurality of delayed first clock signal inputs lead the second clock signal input;
• and
• phase lag measurement means for detecting whether the plurality of delayed second clock signal inputs lead the first clock signal input.

A phase-locked loop comprising:

• a phase detector having a clock input, a feedback input, and a charge control output;
• a charge pump coupled to the charge control output;
• a loop filter coupled to the charge pump;
• a voltage controlled oscillator having a control voltage input coupled to the loop filter and a clock output coupled to the feedback input;
• and
• a phase lock detector comprising:
• a phase lead detector comprising a phase lead latch having a data input coupled to the feedback input, a latch control input coupled to the clock input, a data output and a phase lead delay from the feedback input to the data output, which represents a threshold phase difference between the feedback input and the clock input under which the phase-locked loop is in a lock state, wherein the data output of the phase lead latch has a first logic state when the feedback input leads the clock input by less than the phase lead delay and a second, opposite logic state when the feedback input leads the clock input by more than the phase lead delay;
• a phase lag detector comprising a phase lag latch having a data input coupled to the clock input, a latch control input coupled to the feedback input, a data output and a phase lag delay from the clock input to the data output, which represents the threshold phase difference, wherein the data output of the phase lag latch has the first logic state when the feedback input lags the clock input by less than the phase lag delay and the second logic state when the feedback input lags the clock input by more than the phase lag delay;
• and
• a phase lock signal generator, which comprises a counter circuit, which is coupled to the data outputs of the phase lead and phase lag latches for counting a duration in which either of the data outputs is in the first logic state and responsively generates a phase lock signal indicative of whether the phase-locked loop is in the lock state.

A method of measuring phase error between first and second clock signals on an integrated circuit, the method comprising:

• delaying the first clock signal by a plurality of different phase lead delays to produce a plurality of delayed first clock signals;
• latching the delayed first clock signals as a function of the second clock signal to produce a phase lead indicating output signal;
• delaying the second clock signal by a plurality of different phase lag delays to produce a plurality of delayed second clock signals;
• latching the delayed second clock signals as a function of the first clock signal to produce a phase lag indicating output signal;
• and
• generating signal indicative of the phase error between the first and second clock signals relative to the phase lead delays and the phase lag delays based on the phase lead indicating output and the phase lag indicating output.