Rescheduling data input and output commands for bus synchronization by using digital latency shift detection

A digital latency shift detection means comprising:

• a clock compensation circuit generating a compensated clock signal with respect to a first clock signal by a first delay time (t) defined by a first delay element;
• a frequency divider circuit coupling said clock for generating a second clock signal having a frequency one-half the frequency of said clock;
• a second delay element coupled to said second clock signal and generating a third clock signal which is delayed by said first delay time (t1) plus a second delay time (t2);
• and
• a detection circuit for detecting when a leading edge transition of said third clock signal occurs before a trailing edge transition of said second clock signal, thereby detecting a digital latency shift of odd cycles due to said clock compensation.

A digital latency shift detection means comprising:

• a clock compensation circuit that generates a compensated clock signal with respect to a first clock signal by a first delay time (t1) defined by a first delay element;
• a plurality (m) of frequency divider circuits, each being coupled to said first clock signal for generating second clock signals having a frequency equal to ½m frequency of said clock;
• a plurality (m) of second delay elements, each of said delay elements being coupled to each of said corresponding second clock signals, generating third clock signals that are delayed by said the first delay time (t1) plus a second delay time (t2);
• and
• a plurality (m) of detection circuits, each of said detection circuits generating a corresponding detect signal output (DETECTi), wherein i is an integer ranging from 1 to m, and wherein when a leading edge transition of said third clock signal occurs before a trailing edge transition of a corresponding one of said second clock signals, a multiple digital shift condition up to m cycles is determined by the result of said detection (DETECTi).

A digital latency shift detection means comprising:

• a clock compensation circuit generating a compensated clock with respect to a first clock signal by a first delay time (t1) defined by a first delay element;
• a first plurality (m) of edge-triggered delay latch circuits (D-LATCHi), wherein i is an integer ranging from 0 to m−1, each of said D-LATCHi's having a corresponding input port Di and corresponding output port Qi generating corresponding output signals Si synchronized to said first clock signal, wherein edge-triggered delay latch D-LATCH0 is responsive to an enable signal to initiate a digital latency shift detection, and output signal S0 is coupled to a second delay element to generate a second clock signal which is delayed by said first delay time (t1) plus a second delay time (t2), and output signal Si (i>0) is coupled to the Di+1 port to generate output signal Si+1 signal;
• and
• a second plurality of edge-triggered delay latch circuits (D-LATCHj), wherein j is integer ranging from 0 to m−1, each of said D-LATCHj's having a corresponding input ports Dj and the corresponding output ports Qj, a corresponding input port Dj coupled to output signal Si, and a corresponding output port Qj generating a detection result signal SHIFTj synchronized to said second clock signal, wherein a shift condition of m cycles is determined by the outcome of said detection result signal SHIFTj.