Method and apparatus for configuring and initializing a memory device and a memory channel
AssigneeIntel Corporation
InventorsWilliam A. Stevens, Puthiya K. Nizar
Life of this patent
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Abstract
A method and apparatus for configuring and/or initializing memory devices. A disclosed method initializes a memory controller and a plurality of memory controller configuration registers. Serial identification numbers are assigned to memory devices coupled to the memory controller. Additionally, groups of device identification numbers, which are based at least in part on the memory device sizes, are assigned to the memory devices, and the memory devices are enabled.
Claims20
A method comprising:
- assigning device identification numbers to groups of a plurality of memory devices based at least in part on memory device sizes by:
- assigning a set of lowest identification numbers to memory devices having a largest supported size;
- and
- assigning subsequent identification numbers to remaining memory devices having smaller sizes;
- programming registers in each of the plurality of memory devices to equalize a sum of a device response time and a propagation delay from each memory device to a memory controller for all of the plurality of memory devices.
A method comprising:
- assigning device identification numbers to groups of a plurality of memory devices based at least in part on memory device sizes by:
- determining device size information for each of a plurality of memory modules;
- selecting a selected memory module based on its device size;
- assigning device identification numbers to at least one group of devices on the selected memory module;
- and
- repeating selecting a next selected memory module and assigning device identification numbers until all devices have device identification numbers;
- programming registers in each of the plurality of memory devices to equalize a sum of a device response time and a propagation delay from each memory device to a memory controller for all of the plurality of memory devices.
A system comprising:
- a processor;
- a memory controller coupled to processor, the memory controller having a plurality of control registers and a serial interface circuit;
- a memory bus having a plurality of memory devices coupled thereto, the memory bus being coupled to the memory controller;
- an additional memory device coupled to the memory controller, the additional memory device being accessible to the memory controller prior to initializing the plurality of memory devices, the additional memory device containing a plurality of instructions which, if executed by the system, cause the system to perform operations comprising:
- assigning device identification numbers to the plurality of memory devices based at least in part on memory device sizes by:
- assigning a set of lowest identification numbers to memory devices having a largest supported size;
- and
- assigning subsequent identification numbers to remaining memory devices having smaller sizes.
The system of claim 8 further comprising:
- battery backed lip memory to store a plurality of powerdown restore values.
- 11.The system of claim 10 wherein said operations further comprise:
- restoring the plurality of powerdown restore values upon exit of a low power state.
The system of claim 11 wherein said operations further comprise:
- storing said plurality of powerdown restore values in the battery backed up memory prior to starting normal operation after initial system reset.
An article comprising a machine readable medium having stored thereon a plurality of instructions which, if executed by a machine, cause the machine to perform operations comprising:
- assigning device identification numbers to the plurality of memory devices based at least in part on memory device sizes by:
- assigning a set of lowest identification numbers to memory devices having a largest supported size;
- and
- assigning subsequent identification numbers to remaining memory devices having smaller sizes;
- programming registers in each of the plurality of memory devices to equalize a sum of a device response time and a propagation delay from each memory device to a memory controller for all of the plurality of memory devices.
Dependencies are inferred from the claim text.