Computer architecture for shared memory access

A multiple processor computer configured to use a storage system, the computer comprising a plurality of memory access units, including:

• a first memory access unit responsive to execution of instructions by a first instruction processor, wherein the first memory access unit is coupled to the storage system;
• and
• a second memory access unit responsive to execution of instructions by a second instruction processor, wherein the second memory access unit is coupled to the storage system;
• wherein the first and the second memory access units are each capable of issuing memory access messages to the storage system and receiving return messages from the storage system in response to the memory access messages, the memory access messages and return messages including:
• a first memory access message that specifies a first address and a first value for causing the first value to be stored at a first location in storage system that is associated with the first address;
• a first return message that is a response to the first memory access message, indicating that the first value has been stored in the storage system at a location that is associated with the first address and that is accessible to the one of the memory access units that received the first return message;
• a second return message indicating that the first value has been stored in the storage system at a location that is associated with the first address and that is accessible to each of the plurality of memory access units.

A method for providing data storage for a plurality of computer processors in a memory system that includes a plurality of local storages, including a first local storage unit and other local storage units, the method comprising:

• receiving at the first local storage a first message from a corresponding one of the plurality of computer processors, wherein the first message specifies a first address and a first value;
• processing the first message by the first local storage unit including storing the first value at a location in the local storage unit that is associated with the first address, such that, for at least a period of time, the other local storage units do not have access to the first value;
• receiving at the first local storage a second message from the corresponding one of the plurality of computer processors, wherein the second message specifies the first address;
• processing the second message by the first local storage unit after processing the first message such that the processing of the second message completes after the first value can be accessed by each of the other local storage units.

A computer system comprising:

• a hierarchical memory system, including a first local storage, and a main storage;
• and
• a first memory access unit coupled to the hierarchical memory system capable of processing a plurality of memory access instructions that includes
• (a) a first instruction that specifies a first address and a first value, wherein processing the first instruction by the first memory access unit causes the first value to be stored at a location in the first local storage that is associated with the first address,
• (b) a second instruction that specifies the first address, wherein processing of the second instruction by the first memory access unit after processing the first instruction is such that the first memory access unit complete processing of the second instruction after the first value is stored at a location in the main storage that is associated with the first address,
• (c) a third instruction that specifies the first address, wherein processing of the third instruction by the first memory access unit causes a value to be retrieved from a location in the first local storage that is associated with the first address, and
• (d) a fourth instruction that specifies the first address, wherein processing of the fourth instruction by the first memory access unit prior to processing the third instruction causes the value retrieved during processing the third instruction to be a value that was retrieved from a location in the main storage that is associated with the first address at a time after the fourth instruction was begun to be processed.

A computer system comprising:

• a hierarchical memory system, including a first local storage, a second local storage, and a main storage;
• and
• a first memory access unit coupled to the hierarchical memory system capable of processing a plurality of memory access instructions that includes
• (a) a first instruction that specifies a first address and a first value, wherein processing the first instruction by the first memory access unit causes the first value to be stored at a location in the first local storage that is associated with the first address, and
• (b) a second instruction that specifies the first address, wherein processing of the second instruction by the first memory access unit after processing the first instruction is such that the first memory access unit complete processing of the second instruction after the first value is stored at a location in the main storage that is associated with the first address;
• and
• a second memory access unit coupled to the hierarchical memory system capable of processing the plurality of memory access, and the plurality of instructions further includes
• (c) a third instruction that specifies the first address, wherein processing of the third instruction by the second memory access unit causes a value to be retrieved from a location in the second local storage that is associated with the first address, and
• (d) a fourth instruction that specifies the first address, wherein processing of the fourth instruction by the second memory access unit prior to processing the third instruction and after the first memory access unit has completed processing the second instruction causes the value retrieved during processing the third instruction to be a value that was retrieved from a location in the main storage that is associated with the first address at a time after the fourth instruction was begun to be processed, whereby the value caused to be retrieved by the processing of the third instruction by the second memory access unit is the first value, which was specified in the first instruction which was processed by the first memory access unit.

A computer processor for use in a multiple processor system in which the computer processor is coupled to one or more other processors through a memory system, the computer processor comprises a memory access unit configured to access the memory system by processing a plurality of memory access instructions, including

• (a) a first instruction that specifies a first address and a first value, wherein processing the first instruction causes the first value to be stored at a location in the memory system that is associated with the first address, such that for at least some period of time the one or more other processors do not have access to the first value;
• (b) a second instruction that specifies the first address, wherein processing of the second instruction after processing the first instruction is such that the processing of the second instruction completes after the first value is accessible to each of the one or more other processors;
• (c) a third instruction that specifies a second address, wherein processing of the third instruction causes a value to be retrieved from a location in the memory system that is associated with the second address;
• and
• (d) a fourth instruction that specifies the second address, wherein processing of the fourth instruction prior to processing the third instruction causes the third instruction to retrieve a value that was previously stored in the memory system by one of the one or more other processors.

A method for accessing a memory system from a processor in a multiple processor computer system, comprising:

• (a) in a first processor that is coupled to a first local storage in the memory system, processing a first instruction that specifies a first address and a first value, including storing the first value at a location in the first local storage that is associated with the first address,
• (b) in the first processor, after processing the first instruction, processing a second instruction that specifies the first address, wherein processing of the second instruction completes after the first value is stored at a location in a shared storage in the memory system that is associated with the first address,
• (c) in a second processor that is coupled to a second local storage in the memory system, processing a third instruction that specifies the first address, including retrieving a value from a location in the second local storage that is associated with the first address, and
• (d) in the second processor, processing a fourth instruction that specifies the first address prior to processing the third instruction and after the first processor has completed processing the second instruction, including retrieving the first value from the location in the shared storage that is associated with the first address and storing the first value at a location in the second local storage that is associated with the first address, whereby the value retrieved in the processing of the third instruction is the first value, which was specified in the first instruction.