System for handling coherence protocol races in a scalable shared memory system based on chip multiprocessing

A multiprocessor computer system comprising a plurality of nodes, each node from said plurality of nodes comprising:

• an interface to a local memory subsystem, the local memory subsystem storing a multiplicity of memory lines of information and a directory;
• a first memory cache for caching memory lines of information, said memory lines of information including memory lines of information stored in the local memory subsystem and memory lines of information stored in a remote memory subsystem that is local to another node;
• a protocol engine configured to maintain cache coherence across the plurality of nodes;
• a cache controller configured to maintain cache coherence within the node;
• the protocol engine configured transmit an external request concerning a memory line of information to the cache controller for processing and a response, the external request originating from another node;
• the cache controller configured to transmit an internal request concerning the memory line of information to the protocol engine for processing and a response, the internal request originating from the first memory cache;
• the protocol engine configured to process the transmitted internal request, if a memory transaction corresponding to the transmitted internal request and a memory transaction corresponding to the transmitted external request overlap, by
• sending an instruction request to the cache controller for a set of one or more instructions concerning the transmitted internal request;
• and
• stalling action on the transmitted internal request until after the set of one or more instructions is received.