System and method for caching data based on identity of requestor

A method for caching data retrieved from working memory of a computer system in response to a request by a system resource in said computer system, said method comprising:

• receiving a memory request from said system resource;
• appending a source tag, identifying said system resource, to said memory request;
• processing said memory request to determine, based on said source tag, whether the result of said memory request is to be cached;
• wherein:
• said processing comprises comparing said source tag to a stored list of source tags identifying resources whose requests should be cached.

A method for caching data retrieved from working memory of a computer system in response to a request by a system resource in said computer system, said method comprising:

• receiving a memory request from said system resource;
• appending a source tag, identifying said system resource, to said memory request;
• processing said memory request to determine, based on said source tag, whether the result of said memory request is to be cached;
• wherein:
• said system resources are distributed in said system in a hierarchy;
• said memory request travels through said hierarchy;
• and
• said appending comprises adding respective portions of said tag at respective points as said memory request travels through said hierarchy.

A computer system comprising:

• working memory;
• a plurality of system resources submitting memory requests to said working memory;
• source tag circuitry for adding to each said memory request a source tag that identifies which of said system resources has made said memory request;
• cache control circuitry for determining, based on said source tag, whether the result of a particular memory request is to be cached;
• and
• a level-three cache;
• wherein:
• when said system resource making said memory request is an input/output resource, said result is cached in said level-three cache.

A computer system comprising:

• working memory;
• a plurality of system resources submitting memory requests to said working memory;
• source tag circuitry for adding to each said memory request a source tag that identifies which of said system resources has made said memory request;
• and
• cache control circuitry for determining, based on said source tag, whether the result of a particular memory request is to be cached;
• wherein:
• said cache control circuitry comprises registers storing a list of source tags identifying system resources the results of whose memory requests are to be cached.

A computer system comprising:

• working memory;
• a plurality of system resources submitting memory requests to said working memory;
• source tag circuitry for adding to each said memory request a source tag that identifies which of said system resources has made said memory request;
• and
• cache control circuitry for determining, based on said source tag, whether the result of a particular memory request is to be cached;
• wherein:
• said system resources are distributed in said system in a hierarchy;
• said system includes switch elements through which said memory request travels between levels of said hierarchy;
• and
• each of said switch elements adds a respective portion of said tag at respective points as said memory request travels through said hierarchy.

A logic chipset for use in a computer system, said computer system having at least one system resource on at least one bus, and having working memory of which said at least one system resource makes requests, said chipset comprising:

• a microprocessor chip;
• and
• an interface chip for communicating between said microprocessor chip and said at least one bus;
• source tag circuitry on said interface chip for adding to each said memory request a source tag that identifies which of said system resources has made said memory request;
• and
• cache control circuitry for determining, based on said source tag, whether the result of a particular memory request is to be cached;
• wherein:
• said cache control circuitry comprises registers storing a list of source tags identifying system resources the results of whose memory requests are to be cached.

A logic chipset for use in a computer system, said computer system having at least one system resource on at least one bus, and having working memory of which said at least one system resource makes requests, said chipset comprising:

• a microprocessor chip;
• and
• an interface chip for communicating between said microprocessor chip and said at least one bus;
• source tag circuitry on said interface chip for adding to each said memory request a source tag that identifies which of said system resources has made said memory request;
• and
• cache control circuitry for determining, based on said source tag, whether the result of a particular memory request is to be cached;
• wherein:
• said system resources are distributed in said system in a hierarchy;
• said interface chip includes switch elements through which said memory request travels between levels of said hierarchy;
• and
• said source tag circuitry comprises said switch elements, each of said switch elements adding a respective portion of said tag at respective points as said memory request travels through said hierarchy.

A logic chipset for use in a computer system, said computer system having at least one system resource on at least one bus, and having working memory of which said at least one system resource makes requests, said chipset comprising:

• a microprocessor chip;
• and
• an interface chip for communicating between said microprocessor chip and said at least one bus;
• source tag circuitry on said interface chip for adding to each said memory request a source tag that identifies which of said system resources has made said memory request;
• and
• cache control circuitry for determining, based on said source tag, whether the result of a particular memory request is to be cached;
• wherein:
• said interface chip is a northbridge chip;
• and
• said cache control circuitry comprises registers storing a list of source tags identifying system resources the results of whose memory requests are to be cached.

A logic chipset for use in a computer system, said computer system having at least one system resource on at least one bus, and having working memory of which said at least one system resource makes requests, said chipset comprising:

• a microprocessor chip;
• and
• an interface chip for communicating between said microprocessor chip and said at least one bus;
• source tag circuitry on said interface chip for adding to each said memory request a source tag that identifies which of said system resources has made said memory request;
• and
• cache control circuitry for determining, based on said source tag, whether the result of a particular memory request is to be cached;
• wherein:
• said interface chip is a northbridge chip;
• said system resources are distributed in said system in a hierarchy;
• said interface chip includes switch elements through which said memory request travels between levels of said hierarchy;
• and
• said source tag circuitry comprises said switch elements, each of said switch elements adding a respective portion of said tag at respective points as said memory request travels through said hierarchy.

A computer system comprising:

• working memory means;
• a plurality of system resources submitting memory requests to said working memory means;
• source tag means for adding to each said memory request a source tag that identifies which of said system resources has made said memory request;
• cache control means for determining, based on said source tag, whether the result of a particular memory request is to be cached;
• and
• a level-three cache;
• wherein:
• when said system resource making said memory request is an input/output resource, said result is cached in said level-three cache.

A computer system comprising:

• working memory means;
• a plurality of system resources submitting memory requests to said working memory means;
• source tag means for adding to each said memory request a source tag that identifies which of said system resources has made said memory request;
• and
• cache control means for determining, based on said source tag, whether the result of a particular memory request is to be cached;
• wherein:
• said cache control means comprises registers storing a list of source tags identifying system resources the results of whose memory requests are to be cached.

A computer system comprising:

• working memory means;
• a plurality of system resources submitting memory requests to said working memory means;
• source tag means for adding to each said memory request a source tag that identifies which of said system resources has made said memory request;
• and
• cache control means for determining, based on said source tag, whether the result of a particular memory request is to be cached;
• wherein:
• said system resources are distributed in said system in a hierarchy;
• said system includes switch means through which said memory request travels between levels of said hierarchy;
• and
• each of said switch means adds a respective portion of said tag at respective points as said memory request travels through said hierarchy.

A logic chipset for use in a computer system, said computer system having at least one system resource on at least one bus means, and having working memory means of which said at least one system resource makes requests, said chipset comprising:

• microprocessor chip means;
• and
• interface chip means for communicating between said microprocessor chip means and said at least one bus means;
• source tag means on said interface chip means for adding to each said memory request a source tag that identifies which of said system resources has made said memory request;
• and
• cache control means for determining, based on said source tag, whether the result of a particular memory request is to be cached;
• wherein:
• said cache control means comprises register means storing a list of source tags identifying system resources the results of whose memory requests are to be cached.

A logic chipset for use in a computer system, said computer system having at least one system resource on at least one bus means, and having working memory means of which said at least one system resource makes requests, said chipset comprising:

• microprocessor chip means;
• and
• interface chip means for communicating between said microprocessor chip means and said at least one bus means;
• source tag means on said interface chip means for adding to each said memory request a source tag that identifies which of said system resources has made said memory request;
• and
• cache control means for determining, based on said source tag, whether the result of a particular memory request is to be cached;
• wherein:
• said system resources are distributed in said system in a hierarchy;
• said interface chip means includes switch means through which said memory request travels between levels of said hierarchy;
• and
• said source tag means comprises said switch means, each of said switch means adding a respective portion of said tag at respective points as said memory request travels through said hierarchy.

A logic chipset for use in a computer system, said computer system having at least one system resource on at least one bus means, and having working memory means of which said at least one system resource makes requests, said chipset comprising:

• microprocessor chip means;
• and
• interface chip means for communicating between said microprocessor chip means and said at least one bus means;
• source tag means on said interface chip means for adding to each said memory request a source tag that identifies which of said system resources has made said memory request;
• and
• cache control means for determining, based on said source tag, whether the result of a particular memory request is to be cached;
• wherein:
• said interface chip means is a northbridge chip;
• said cache control means comprises register means storing a list of source tags identifying system resources the results of whose memory requests are to be cached.

A logic chipset for use in a computer system, said computer system having at least one system resource on at least one bus means, and having working memory means of which said at least one system resource makes requests, said chipset comprising:

• microprocessor chip means;
• and
• interface chip means for communicating between said microprocessor chip means and said at least one bus means;
• source tag means on said interface chip means for adding to each said memory request a source tag that identifies which of said system resources has made said memory request;
• and
• cache control means for determining, based on said source tag, whether the result of a particular memory request is to be cached;
• wherein:
• said interface chip means is a northbridge chip;
• said system resources are distributed in said system in a hierarchy;
• said interface chip means includes switch means through which said memory request travels between levels of said hierarchy;
• and
• said source tag means comprises said switch means, each of said switch means adding a respective portion of said tag at respective points as said memory request travels through said hierarchy.