Hardware prefetch system based on transfer request address of cache miss load requests
AssigneeHitachi, Ltd.
InventorTomohiro Nakamura
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Abstract
The data-transfer latency of a cache-miss load instruction is shortened in a processor having a cache memory. A load history table wherein a transfer address of the cache-miss load instruction is registered is provided between the processor and a memory system. When access addresses are sequential, a request for hardware prefetch to a successive address is issued and the address is registered into a prefetch buffer. Further, when a cache-miss load request to the successive address is issued, the data are transferred from the prefetch buffer directly to the processor. The system may include multiple simultaneous prefetches and a prefetch variable optimized using software.
Claims14
A prefetch system in a computer system having a processor, a cache memory, and a main memory, the prefetch system comprising:
- means for setting a variable indicating a prefetch interval into a register in accordance with a software being executed in said computer system;
- a load history table adapted to store a plurality of previous transfer request addresses of cache miss load requests issued by said processor;
- a first comparator for comparing a present transfer request address of a present cache miss load request with said previous transfer request addresses stored in the load history table plus a constant;
- a second comparator for comparing said present transfer request address with said previous transfer request addresses stored in the load history table minus the constant;
- and
- transfer-requesting means for generating a data transfer request which designates a prefetch target address to prefetch data therefrom if any of comparison results of said first and second comparators is true and for sending the data transfer request to the main memory, wherein said prefetch target address is equal to said present transfer request address plus said prefetch interval if a comparison result of said first comparator is true and said prefetch target address is equal to said present transfer request address minus said prefetch interval if a comparison result of said second comparator is true.
A hardware prefetch method for a computer system including a processor, a cache memory, and a main memory, said prefetch method comprising the steps of:
- setting a variable into a register according to a prefetch interval indicated in a software being executed in said computer system;
- receiving a cache miss load request address as a present transfer request address;
- comparing said present transfer request address to a plurality of previous transfer request addresses stored in a load history table plus a constant and to said plurality of previous transfer request addresses stored in the load history table minus the constant;
- generating a prefetch request designating a prefetch target address to prefetch data therefrom if any of the comparison results in said comparing step is true, wherein said prefetch target address is equal to said present transfer request address plus said prefetch interval if said present transfer request address coincides with one of said previous transfer request addresses plus the constant, and said prefetch target address is equal to said present transfer request address minus said prefetch interval if said present transfer request address coincides with one of said previous transfer request addresses minus the constant;
- and
- sending said generated prefetch request to the main memory.
Dependencies are inferred from the claim text.