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AssigneeRambus Inc.
InventorsFrederick A. Ware, Richard E. Perego, Craig E. Hampel, Ely K. Tsern
Estimating the term…
Techniques for increasing bandwidth in port-per-module memory systems having mismatched memory modules are disclosed. In one exemplary embodiment, the techniques are realized through a memory component having a memory core for storing data therein. The memory component comprises a first set of interface connections for providing access to the memory core, and a second set of interface connections for providing access to the memory core. The memory component also comprises memory access circuitry for selecting between a first mode wherein a first portion of the memory core is accessible through the first set of interface connections and a second portion of the memory core is accessible through the second set of interface connections, and a second mode wherein both the first portion and the second portion of the memory core are accessible through the first set of interface connections.
A memory component having a single port memory core for storing data therein, the memory component comprising:
A method for accessing a single port memory core of a memory component, the memory component having first and second sets of interface connections for providing access to the single port memory core, the method comprising the steps of:
A memory component having a single memory core device for storing data therein, the memory component comprising:
A method for accessing a single memory core device of a memory component, the memory component having first and second sets of interface connections for providing access to the single memory core device, the method comprising the steps of:
Dependencies are inferred from the claim text.