Shared memory multiprocessor performing cache coherence control and node controller therefor

A shared memory multiprocessor comprising:

• a plurality of nodes each configured with at least one of a processor having a cache memory, a memory device and an I/O device, and a node controller;
• and
• an inter-node connection network for interconnecting a plurality of said nodes;
• wherein at least one of a plurality of said nodes includes said processor and at least one each of said memory device and said I/O device, and the whole of a plurality of said nodes include at least one said processor, at least one said memory device and at least one said I/O device;
• wherein said node controller of each of a plurality of said nodes includes a processor unit constituting an interface with said processor in the local node, a memory unit constituting an interface with said memory device in the local node and/or an I/O unit constituting an interface with said I/O device in the local node, a network unit constituting an interface with said inter-node connection network, and an intra-node connection circuit for connecting said processor unit, at least one of said memory device and said I/O device, and said network unit;
• wherein said processor unit includes an inter-unit address decode circuit and a cache coherence control circuit,
• said inter-unit address decode circuit decoding the control information and the address information in said access request, and operating in such a manner that the information on the node associated with the memory unit or the I/O unit intended as an access request destination, the information on the unit intended as an access request destination, and the cache coherence control information indicating whether the cache coherence control is required or not, are added to a memory access request or an I/O access request issued by the processor in the local node,
• said cache coherence control unit performing the cache coherence control of the processor in the local node in the case where the cache coherence control information added to the access request received from said network unit indicates that the cache coherence control is required,;
• wherein said I/O unit includes an inter-unit address decode circuit for adding the node information and the unit information for the memory unit or the I/O unit intended as an access request destination and the cache coherence control information indicating whether the cache coherence control is required or not, to the memory access request or the I/O access request issued by the I/O device in the local node;
• wherein said network unit includes a transfer unit for transferring the access request received from said intra-node connection circuit to said inter-node connection network, and a transfer unit for transferring the access request transferred thereto from said inter-node connection network to said intra-node connection network;
• wherein said intra-node connection circuit operates in such a manner that in the case where a unit in the local node is designated as the destination of transfer based on the cache coherence control information, the node information and the unit information added to the access request transferred from said inter-node connection network through said network unit, said access request is transferred to the unit designated as the transfer destination;
• wherein said intra-node connection circuit includes a unit designation circuit for designating the destination of transfer of said access request based on the cache coherence control information, the node information and the unit information added to the access request transferred from said inter-node connection network, and a transfer unit for transferring said access request to the unit connected to said intra-node connection circuit in response to the designation of said unit designation circuit;
• wherein said inter-node connection network includes a node designation circuit for designating the destination of transfer of said access request based on the cache coherence control information, the node information and the unit information added to the access request sent out from said network unit, and a transfer unit for transferring said access request in response to the designation of said node designation circuit;
• and
• wherein that access request issued by said processor or said I/O device which requires the cache coherence control is broadcast to all the nodes requiring the cache coherence control, while the access request not requiring the cache coherence control is transferred only to the node intended as a destination.

A node controller included in each node of a shared memory multiprocessor comprising

• a plurality of nodes each configured with at least one of a processor having a cache memory, a memory device and an I/O device, and a node controller, and
• an inter-node connection network for interconnecting a plurality of said nodes;
• wherein at least one of a plurality of said nodes includes said processor and at least one each of said memory device and said I/O device, and the whole of a plurality of said nodes include at least one said processor, at least one said memory device and at least one said I/O device;
• wherein said node controller of each of a plurality of said nodes includes a processor unit constituting an interface with said processor in the local node, at least one of a memory unit constituting an interface with said memory device in the local node and an I/O unit constituting an interface with said I/O device in the local node, a network unit constituting an interface with said inter-node connection network, and an intra-node connection circuit for connecting said processor unit, at least one of said memory device and said I/O device, and said network unit to each other;
• wherein said processor unit includes an inter-unit address decode circuit and a cache coherence control circuit,
• said inter-unit address decode circuit decoding the control information and the address information in said access request, and operating in such a manner that the information on the node associated with the memory unit or the I/O unit intended as an access request destination, the information on the unit intended as an access request destination, and the cache coherence control information indicating whether the cache coherence control is required or not, are added to a memory access request or an I/O access request issued by the processor in the local node
• said cache coherence control circuit performing the cache coherence control of the processor in the local node in the case where said cache coherence control information added to the access request received from said network unit indicates that the cache coherence control is required;
• wherein said I/O unit includes an inter-unit address decode circuit for adding the node information and the unit information for the memory unit or the I/O unit intended as an access request destination and the cache coherence control information indicating whether the cache coherence control is required or not, to the memory access request or the I/O access request issued by the I/O device in the local node;
• wherein said network unit includes a transfer unit for transferring the access request received from said intra-node connection circuit to said inter-node connection network, and a transfer unit for transferring the access request transferred thereto from said inter-node connection network to said intra-node connection network;
• wherein said intra-node connection circuit includes a route designation circuit for designating the destination of transfer of the access request transferred from said inter-node connection network, based on the cache coherence control information, the node information and the unit information added to said access request, and a transfer unit for transferring said access request to a unit connected to said intra-node connection circuit in response to the designation of said route designation circuit;
• and
• wherein that access request issued by said processor or said I/O device which requires the cache coherence control is broadcast to all the nodes requiring the cache coherence control, and the access request not requiring the cache coherence control is transferred only to the node intended as a destination.

A shared memory multiprocessor comprising:

• a plurality of nodes each configured with at least one of a processor having a cache memory, a memory device and an I/O device;
• and
• an inter-node connection network for interconnecting a plurality of said nodes;
• wherein at least one of a plurality of said nodes includes said processor and at least one each of said memory device and said I/O device, and the whole of a plurality of said nodes include at least one said processor, at least one said memory device and at least one said I/O device;
• wherein each of a plurality of said nodes includes an information adding unit for adding the cache coherence control information indicating whether the cache coherence control is required or not and the node information indicating the node constituting a destination of transfer (destination of access), to the access request issued by said processor or said I/O device in the local node, and outputting the resulting information, and a transfer unit for selectively transferring the access request from said information adding unit to said inter-node connection network;
• and
• wherein said inter-node connection network includes a transfer unit which, based on said cache coherence control information and said node information added to the access request, transfers said access request to all the nodes requiring the cache coherence control among a plurality of said nodes in the case where said cache coherence control information indicates that the cache coherence control is required, and transfers said access request only to the node indicated by the node information added to said access request in the case where said cache coherence control information indicates that the cache coherence control is not required.