Bus interface circuit preparation apparatus and recording medium

A bus interface circuit preparation apparatus, which outputs a hardware description language expressing said bus interface circuit by inputting a description of a bus interface including a memory element which is disposed between a central processing unit constituting a master and hardware constituting a slave for said central processing unit, comprising:

• an RW address comparison portion for determining whether a reading global address and a writing global address, both allocated to the same memory element, are identical, based on the inputted bus interface description;
• a determination portion for determining whether or not said reading global address and said writing global address are divided to form different addresses in the bit unit;
• and
• a select signal generating circuit for outputting the select signal which becomes active when said global address is assigned, providing that said reading global address and said writing global address are identical and that said global addresses are different addresses in the bit unit, and a circuit generating portion for generating conversion circuits corresponding to each of said global addresses for converting said global addresses to local addresses of said memory element.

A bus interface circuit preparation apparatus, which outputs a hardware description language expressing said bus interface circuit by inputting a description of a bus interface including a memory element which is disposed between a central processing unit constituting a master and hardware constituting a slave for said central processing unit, comprising:

• an RW address comparison portion for determining whether a reading global address and a writing global address, both allocated to the same memory element, are identical;
• a determination portion for determining whether said reading global address and said writing global address are divided to form different addresses in the bit unit;
• and
• a select signal generating circuit for outputting the select signal which becomes active when said global address is assigned, providing that said reading global address and said writing global address are different addresses and that respective addresses of said reading global address are identical to said writing global address, and a circuit generating potion for generating conversion circuits corresponding to said writing global address and said writing global address for converting said global addresses to local addresses of said memory element.

A bus interface circuit preparation apparatus, which outputs a hardware description language expressing said bus interface circuit by inputting a description of a bus interface including a memory element which is disposed between a central processing unit constituting a master and hardware constituting a slave for said central processing unit, comprising:

• an RW address comparison portion for determining whether or not a reading global address and a writing global address, both allocated to the same memory element, are identical;
• a determination portion for determining whether said reading global address and said writing global address are divided to form different addresses in the bit unit;
• and
• a select signal generating circuit for outputting the select signal which becomes active when any one of said reading global address and said writing global address, which form different addresses in the bit unit, is assigned, provided that said reading global address and said writing global address are different addresses and that at least any one of said reading global address and said writing global address forms different addresses in the bit unit, and a circuit generating portion for generating conversion circuits corresponding to each of said reading global addresses and to each of said writing global addresses for converting said global address to local addresses of said memory element.

A bus interface circuit preparation apparatus, which outputs a hardware description language expressing said bus interface circuit by inputting a description of a bus interface including a memory element which is disposed between a central processing unit constituting a master and hardware constituting a slave for said central processing unit, comprising:

• an extracting portion for extracting a top global address and an address range for said memory elements from the inputted bus interface description;
• a calculating portion for calculating the number of the minimum address lines which is capable of assigning any address in said address range extracted by said extracting portion;
• a checker portion for determining whether all of the lower n bits are 0;
• and
• a circuit generating portion for outputting the select signal, using the lower n bits of said global addresses as the address input of said memory element and utilizing said global address values excluding the lower n bits, when said checker portion has determined that all of the lower n bits are 0.

A bus interface circuit preparation apparatus, which outputs a hardware description language expressing said bus interface circuit by inputting a description of a bus interface including a memory element which is disposed between a central processing unit constituting a master and hardware constituting a slave for said central processing unit, comprising:

• an extracting portion for extracting a top global address and tan address range of said memory element from the bus interface description;
• a calculating portion for calculating the number of minimum address lines, capable of assigning individually any address within said address range extracted by said extracting portion;
• a checker portion for determining whether all of the lower n bits are 0;
• and
• a warning portion for warning when 1 is present in said lower n bits.

A computer readable recording medium which stores a bus interface circuit preparation program for outputting a hardware description language expressing said bus interface circuit by inputting a description of a bus interface including a memory element which is disposed between a central processing unit constituting a master and hardware constituting a slave for said central processing unit, wherein the bus interface circuit preparation program operated by a computer comprises:

• an extracting step for extracting data related to the address range of said memory element from the inputting bus interface description;
• a bit data storing step for storing the addresses allocated to said memory element based on the data extracted by said extracting portion;
• an address competition detecting step for detecting duplication of the addresses in the memory element based on the data extracted by said extracting portion and information stored in said bit data storing step;
• and
• a circuit generating step for generating a description of a bus interface that prevents duplication of addresses of the memory element.

A computer readable recording medium which stores a bus interface circuit preparation program for outputting a predetermined hardware description language by inputting a description of a bus interface including a memory element which is disposed between a central processing unit constituting a master and hardware constituting a slave for said central processing unit, wherein the bus interface circuit preparation program comprises;

• an RW address comparing step for determining whether or not a reading global address and a writing global address, both allocated to the same memory element, are identical, based on the inputted bus interface description;
• a determining step for determining whether or not said reading global address and said writing global address are divided to form different addresses in the bit unit;
• and
• a circuit generating step for outputting the select signal when said global address is assigned, providing that said reading global address is identical with said writing global address and that said global addresses are different addresses in the bit unit, and for generating conversion circuits corresponding to each of said global addresses for converting said global addresses to local addresses of said memory element, when necessary;
• a circuit generating step for outputting the select signal which becomes active when any one of said two global addresses are assigned, providing that said reading global address and said writing global address are different addresses and that respective addresses of said reading global address are identical with said writing global address, and for generating conversion circuits corresponding to said reading global address and said writing global address for converting said global addresses to local addresses of said memory element;
• and
• a circuit generating step for generating a select signal generating circuit for outputting the select signal which becomes active when any one of said reading global address and said writing global address, which form different addresses in the bit unit, is assigned, providing that said reading global address and said writing global address are different addresses and that at least any one of said reading global address and said writing global address forms different addresses in the bit unit, and for generating conversion circuits corresponding to each of said reading global address and to each of said writing global address for converting said global addresses to local addresses of said memory element.

A computer readable recording medium which stores a bus interface circuit preparation program for outputting a predetermined hardware description language by inputting a description of a bus interface including a memory element which is disposed between a central processing unit constituting a master and hardware constituting a slave for said central processing unit, wherein the bus interface circuit preparation program comprises;

• an extracting portion for extracting a top global address and an address range of said memory element from the bus interface description;
• a calculating portion for calculating the number of minimum address lines, capable of assigning individually any address within said address range extracted by said extracting portion;
• a checker portion for determining whether all of the lower n bits of the top address of said memory element are 0;
• a circuit generating step for outputting a select signal, by using the lower n bits as an address input of the memory element, when the result of the determination in said check step indicates that the lower n bits of the top global address are all 0;
• and
• a warning step for warning the user when the result of the check step indicates that 1 is present in the lower n bits of the top address.