Methods and apparatus for implementing a host side advanced serial protocol

A host controller chip integrated into a host adapter, the host controller chip being configured to enable communication between a host computer that has the host adapter connected thereto and a peripheral device, comprising:

• a serial cable being configured to interconnect the host adapter to the peripheral device, the serial cable including,
• a first differential pair for data;
• a second differential pair for strobe;
• and
• a pair for ground;
• a PCI bus interface circuit for connecting the host adapter to the host computer;
• host controller registers integrated into the host controller chip to enable configuration of the host adapter for operation, initialize the peripheral device, and enable command transmission to the peripheral device over the serial cable;
• a packet generator/decoder circuit integrated into the host controller chip for polling the peripheral device and for sending and receiving packets to and from the peripheral device, wherein the polling controls a data flow and prevents buffers from being underrun and overrun;
• and
• a serializer/deserializer circuit integrated into the host controller chip for converting parallel data containing ATA/ATAPI commands received from the PCI bus interface circuit and to be sent over the serial cable to the peripheral device into serial data and converting serial data received from the serial cable into parallel data to be sent to the PCI bus interface circuit and to the host computer.

A system for executing data transfers between a host computer and a peripheral device over a serial link, comprising:

• a CPU for setting up a command descriptor block (CDB) with an ATA/ATAPI command and a scatter/gather list in a system memory;
• a pointer register resident in a host controller chip, the CPU being configured to write an address of the CDB into the pointer register;
• a DMA controller for instructing a transfer of the CDB to RAM memory of the host controller chip;
• the host controller chip being configured to send the CDB to a peripheral device over a serial physical cable, the host controller chip further being configured to poll the peripheral device for data packets;
• the device being configured to respond to the poll by sending data packets to the RAM of the host controller chip;
• a data buffer being configured to receive the data packets at the direction of the DMA controller, the data buffer being pointed to the scatter/gather list in the system memory;
• and
• the host controller chip being configured to set up an interrupt status to interrupt the CPU indicative of the receipt of the data packets from the peripheral device.