Method for reducing the settling time in PLL circuits

A PLL circuit with reduced settling time, particularly for use in RF transceivers, comprising:

• a phase comparator, which is cascade-connected to a charge pump circuit and to a filter;
• a digital-analog converter;
• an adder;
• and
• a voltage-controlled oscillator provided by means of a varactor, wherein said digital-analog converter is nonlinear, the output current signal of said converter being input to said adder together with a voltage signal output by said filter, said output current signal of said digital-analog converter being variable according to a law such that the voltage obtained from the output current of said digital-analog converter, added to an output voltage of said filter, is such as to keep said filter voltage constant, in order to reduce the settling time of said PLL circuit when a selected channel changes and wherein said law of variation of the output current of said digital-analog converter is nonlinear.

A PLL circuit, comprising:

• a phase comparator circuit having an input terminal coupled to a clocked signal source, a feedback input terminal, and an output terminal;
• a charge pump circuit having an input terminal connected to the output terminal of the phase comparator, and an output terminal;
• a filter circuit having an input terminal coupled to the output terminal of the charge pump, and an output terminal;
• an adder circuit having a non-inverting input terminal connected to the output terminal of the filter circuit, an inverting input terminal, and an output terminal;
• a voltage-controlled oscillator having an input terminal coupled to the output terminal of the adder circuit, an output terminal, and a feedback output terminal coupled to the feedback input terminal of the phase comparator;
• and
• a digital-analog converter (DAC) having an output terminal coupled to the inverting input terminal of the adder circuit, and an input terminal configured to receive a word signal, the DAC configured to output a non-linear signal having characteristics that are a function of the characteristics of a selected transmitter frequency and that maintain a constant filter circuit output voltage.

A method for reducing settling time in a PLL circuit having a phase comparator cascade-connected to a charged pump circuit, a filter circuit, an adder circuit with DAC input, and a voltage-controlled oscillator having a feedback coupled to the phase comparator, the method comprising:

• determining the signal characteristics of a voltage for controlling the voltage-controlled oscillator as a function of a transmitter channel frequency received at the DAC input in order to maintain the filter output voltage constant;
• providing a non-linear DAC output signal having variations substantially matching the variations of the voltage control signal of the voltage-controlled oscillator;
• and
• generating the voltage control signal for the voltage-controlled oscillator, comprising summing the DAC output signal with the filter output signal to maintain a constant filter output signal voltage and reduce settling time in response to changing channel frequencies in a RF that triggered a format transceiver circuit.

A PLL circuit with reduced settling time, particularly for use in RF transceivers, comprising:

• a phase comparator, which is cascade-connected to a charge pump circuit and to a filter;
• a digital-analog converter;
• an adder;
• and
• a voltage-controlled oscillator provided by means of a varactor, wherein said digital-analog converter is nonlinear, the output current signal of said converter being input to said adder together with a voltage signal output by said filter, said output current signal of said digital-analog converter being variable according to a law such that the voltage obtained from the output current of said digital-analog converter, added to an output voltage of said filter, is such as to keep said filter voltage constant, in order to reduce the settling time of said PLL circuit when a selected channel changes, wherein the output current signal of the digital-analog converter is obtained by raising to the power of two a linear combination of an output current signal of a linear digital-analog converter and of a constant current reference signal.

A PLL circuit with reduced settling time, particularly for use in RF transceivers, comprising:

• a phase comparator, which is cascade-connected to a charge pump circuit and to a filter;
• a digital-analog converter;
• an adder;
• and
• a voltage-controlled oscillator provided by means of a varactor, wherein said digital-analog converter is nonlinear, the output current signal of said converter being input to said adder together with a voltage signal output by said filter, said output current signal of said digital-analog converter being variable according to a law such that the voltage obtained from the output current of said digital-analog converter, added to an output voltage of said filter, is such as to keep said filter voltage constant, in order to reduce the settling time of said PLL circuit when a selected channel changes, wherein the digital-analog converter is configured to receive a digital word in input that has a one-two-one correspondence with the control voltage of the voltage-controlled oscillator in relation to a channel selected in a transceiver.

A PLL circuit, comprising:

• a phase comparator circuit having an input terminal coupled to a clocked signal source, a feedback input terminal, and an output terminal;
• a charge pump circuit having an input terminal connected to the output terminal of the phase comparator, and an output terminal;
• a filter circuit having an input terminal coupled to the output terminal of the charge pump, and an output terminal;
• an adder circuit having a non-inverting input terminal connected to the output terminal of the filter circuit, an inverting input terminal, and an output terminal;
• a voltage-controlled oscillator having an input terminal coupled to the output terminal of the adder circuit, an output terminal, and a feedback output terminal coupled to the feedback input terminal of the phase comparator;
• and
• a digital-analog converter (DAC) having an output terminal coupled to the inverting input terminal of the adder circuit, and an input terminal configured to receive a word signal, the DAC configured to output a signal having characteristics that are a function of the characteristics of a selected transmitter frequency and that maintain a constant filter circuit output voltage, wherein the DAC comprises a linear DAC having an input terminal for receiving a word signal corresponding to a selected transmitter frequency and an output terminal coupled to a summing node, a constant current generator having an output terminal coupled to the summing node, and a translinear circuit with an input terminal coupled to the summing node and an output terminal coupled to the DAC output terminal.

A method for reducing settling time in a PLL circuit having a phase comparator cascade-connected to a charged pump circuit, a filter circuit, an adder circuit with DAC input, and a voltage-controlled oscillator having a feedback coupled to the phase comparator, the method comprising:

• determining the signal characteristics of a voltage for controlling the voltage-controlled oscillator as a function of a transmitter channel frequency received at the DAC input in order to maintain the filter output voltage constant;
• providing a DAC output signal having variations substantially matching the variations of the voltage control signal of the voltage-controlled oscillator, wherein providing a DAC output signal comprises raising to the power of two a linear combination of a constant current reference and of a current signal that originates from a linear digital-analog converter;
• and
• generating the voltage control signal for the voltage-controlled oscillator, comprising summing the DAC output signal with the filter output signal to maintain a constant filter output signal voltage and reduce settling time in response to changing channel frequencies in a RF that triggered a format transceiver circuit.