Cascading PLL units for achieving rapid synchronization between digital communications systems

In a digital communications system including a transmitting device and a receiving device, a clock synchronization system for synchronizing a clock signal from the transmitting device with a clock signal in the receiving device, comprising:

• a transmitting device generating a first clock signal Fa;
• a receiving device generating a second clock signal Fb2;
• the receiving device including a first phase locked loop (PLL) circuit and a second PLL circuit, the first PLL circuit adapted to increase the clock signal Fa by a factor K to produce a clock signal Fak, the second PLL circuit adapted to increase the clock signal Fak by a factor L to produce a clock signal Fbn, the second PLL circuit further adapted to decrease the clock signal Fbn by a factor N to produce the clock signal Fb2;
• and
• the first PLL circuit and the second PLL circuit adapted to adjust the values of K, L, and N such that a frequency lock is achieved between Fa and Fb2, enabling digital communication between the transmitting device and the receiving device without requiring a phase lock between the clock signal Fa and the clock signal Fb2;
• wherein the first PLL circuit further includes:
• a VCO adapted to generate the clock signal Fak;
• a first divider coupled to receive the clock signal Fak and divide the clock signal Fak by the factor K to produce the clock signal Fb1;
• and
• a first PLL having a variable input and a reference input, the first PLL coupled to receive the clock signal Fa at its reference input and coupled to receive the clock signal Fb1 at its variable input, the first PLL operable to control the VCO to achieve a frequency lock between the clock signal Fa and the clock signal Fb1.

In a digital communications system, a method for rapidly achieving synchronization between a first communications device and a second communications device to enable digital communication there between, the method comprising the steps of:

• generating a clock signal Fa using a transmitting device;
• generating a second clock signal Fb2 using a receiving device;
• increasing the clock signal Fa by a factor K to produce the clock signal Fak by using a first phase locked loop (PLL) circuit;
• increasing the clock signal Fak by a factor L to produce a clock signal Fbn by using a second PLL circuit;
• decreasing the clock signal Fbn by a factor N to produce a clock signal Fb2 by using the second PLL circuit;
• adjusting the values of the factors K, L, and N such that a frequency lock is achieved between the clock signal Fa and the clock signal Fb2 without requiring a phase lock between the clock signal Fa and the clock signal Fb2;
• and
• using the clock signal Fb2 to sample a data stream received by the receiving device from the transmitting device;
• wherein the first PLL circuit includes a first PLL having a wide tuning range and adapted to achieve a fast frequency lock.