High-speed digital timing and gain gradient circuit employing a parallel architecture

A system for processing a digital feedback control signal, resulting from processing an incoming signal, having a bit rate frequency, and a separate timing reference signal, the processed feedback signal controlling a synchronization circuit, comprising:

• parallel paths, having stages, for processing the digital feedback signal;
• and
• a structure facilitating cross-referenced processing between said parallel paths,
• wherein the processing on each of said paths is done at half the bit rate frequency of the incoming signal;
• wherein said structure employs:
• an XOR gate on one of said paths and an {overscore (XOR)} gate on the other of said paths;
• an overflow detection circuit in each of said paths;
• an error detection circuit, having an output, in each of said paths;
• a band and overflow detection circuit, having an output, in each of said paths;
• a summer, having an output, for summing said outputs from each of said error detection circuits;
• a multiplexer, having an output, for processing outputs from each of said error detection circuits, said summer, and each of said band and overflow circuits;
• a reference clock, having an output;
• and
• a register for processing said outputs from said multiplexer and said reference clock into a control signal for a timing recovery circuit.

A method for processing a digital feedback control signal, resulting from processing an incoming signal, having a bit rate and a separate reference signal, the processed feedback control signal controlling a synchronization circuit, comprising:

• deploying parallel paths A and B of operation;
• and
• processing the signal on each path while using operations that cross-reference each of said paths to the other of said path;
• wherein said method comprises:
• employing an XOR gate on one of said paths and an {overscore (XOR)} gate on the other of said paths so as to provide a clocked reference from said path A to said path B and a clocked reference from said path B to said path A;
• employing an overflow detection circuit in each of said paths;
• employing an error detection circuit, having an output, in each of said paths;
• employing a band and overflow detection circuit, having an output, in each of said paths;
• summing said outputs from each of said error detection circuits in a summer, having an output;
• processing outputs from each of said error detection circuits in a multiplexer, having an output, said summer, and each of said band and overflow circuits;
• providing a reference signal from a clock;
• and
• processing said outputs from said multiplexer and said reference clock into a control signal for the synchronization circuit.