Despreading circuit
AssigneeKokusai Electric Corporation
InventorsIchiro Imaizumi, Tetsuhiko Miyatani, Shunji Abe, Kenzo Urabe, Hitoshi Kato
Life of this patent
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Abstract
A despreading circuit which can reduce a circuit scale and power consumption is described. The circuit includes an A/D converter which converts a CDMA modulated analog signal to a digital signal of N bits, and a searcher which defects a synchronization phase from high-order small bits of the N bits and outputs synchronozation phase information to a control circuit. The control circuit transmits a signal for allowing despreading to be performed to a sliding correlator based on the phase information. The sliding correlator despreads the N bit digital signal outputted by the A/D converter and outputs the resulting correlation output as a despreading signal.
Claims4
A despreading circuit comprising:
- an A/D converter for receiving a CDMA modulated analog signal and converting the analog signal to a digital signal of N bits to emit an output;
- a searcher for detecting a synchronization phase as a symbol start point of the CDMA modulated analog signal based on a small number of most significant bits which is one or more bits but less than N bit digital signal outputted by said A/D converter to output phase information as signal indicating the synchronization phase;
- a control circuit for outputting a signal for allowing despreading to be performed as a timing for starting the despreading in accordance with the phase information transmitted from said searcher;
- and
- a sliding correlator for receiving the signal for allowing said despreading to be performed, and starting the despreading of the N bit digital signal outputted by said A/D converter to output a correlation output for one symbol time as a demodulated signal;
- wherein the searcher comprises a sample hold circuit comprising flip-flop circuits connected in multiple stages in accordance with the number of chips for, on receiving an input of digital signal, successively transmitting the digital signal to the next flip-flop circuit while holding said digital signal in the flip-flop circuit,
- multipliers for the flip-flop circuits of said sample hold circuit for, when the digital signal held by the flip-flop circuit connected to each multiplier is successively transmitted to the next flip-flop circuit, multiplying the digital signal and the corresponding bit of PN code as separately inputted spread code by each multiplier to emit an output,
- an adder for collectively adding the digital signals outputted by the multipliers to output the correlation output, and
- a PN code register for transmitting the PN code as the spread code to said multipliers.
Dependencies are inferred from the claim text.