Pseudorandom noise generator for WCDMA
AssigneeTexas Instruments Incorporated
InventorSundararajan Sriram
Life of this patent
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Abstract
A circuit is designed with a plurality of logic circuits (370-374) for producing an offset state matrix. The circuit includes a first logic circuit (380-383) coupled to receive N elements of a respective row of a transition matrix and N elements of column of an input state matrix. The first logic circuit produces a multi-bit logical combination of corresponding bits of the respective row and the column. A second logic circuit (390) is coupled to receive the multi-bit logical combination and produces a respective element of the offset state matrix.
Claims40
A plurality of logic circuits for producing an offset state matrix, each logic circuit comprising:
- a first logic circuit coupled to receive N elements of a respective row of a transition matrix and N elements of column of an input state matrix, the first logic circuit producing a multi-bit logical combination of corresponding bits of the respective row and the column;
- and
- a second logic circuit coupled to receive the multi-bit logical combination, the second logic circuit producing a respective element of the offset state matrix.
A circuit, comprising:
- a first matrix generator circuit in a series of matrix generator circuits coupled to receive an input state matrix, another matrix generator circuit in the series arranged to produce an output state matrix, each matrix generator circuit of the series comprising:
- a matrix multiplication circuit coupled to receive a respective input matrix, the matrix multiplication circuit arranged to produce a product of the respective input matrix and a respective stored matrix;
- and
- a multiplex circuit coupled to receive the respective input matrix, the respective product and a respective count signal, the multiplex circuit selectively producing one of the respective input matrix and the respective product in response to the respective count signal.
A circuit, comprising:
- a first matrix generator circuit coupled to receive a first input state matrix and a count signal, the first matrix generator arranged to produce a first output state matrix having an offset from the input state matrix in response to the count signal;
- and
- a plurality of second matrix generator circuits coupled in series, one of the series of second matrix generator circuits coupled to receive the first output state matrix, each second matrix generator circuit producing a respective output state matrix having a predetermined offset from a respective input state matrix.
A circuit for a communication system, comprising:
- a first series of matrix generator circuits, a first matrix generator circuit in the first series coupled to receive a first input state matrix, a second matrix generator circuit in the first series arranged to produce a first output state matrix;
- a second series of matrix generator circuits, a first matrix generator circuit in the second series coupled to receive a second input state matrix, a second matrix generator circuit in the second series arranged to produce a second output state matrix;
- and
- a logic circuit coupled to the second matrix generator circuit in each of the first and second series, the logic circuit arranged to produce a pseudorandom noise sequence in response to the first output state matrix and the second output state matrix.
A method of generating a matrix, comprising the steps of:
- generating a first matrix having a predetermined number of elements, the first matrix characterized by a first offset;
- generating a second matrix having the predetermined number of elements and different from the first matrix;
- combining elements from the first matrix with elements from the second matrix, thereby producing a third matrix having the predetermined number of elements;
- comparing the first offset with a predetermined value;
- and
- producing one of the first matrix and third matrix in response to the step of comparing.
A method of producing a matrix, comprising the steps of:
- applying a respective plurality of input matrices to a plurality of matrix multiplication circuits;
- applying a plurality of control signals to the plurality of matrix multiplication circuits, each control signal corresponding to a respective matrix multiplication circuit;
- producing a respective output matrix as a product of each respective input matrix and a respective predetermined matrix at each matrix multiplication circuit having a corresponding control signal of a first logic state;
- producing each respective input matrix as a respective output matrix at each matrix multiplication circuit having a corresponding control signal of a second logic state;
- and
- applying more than two of the respective output matrices as the respective input matrices.
Dependencies are inferred from the claim text.