US 6,636,549 B1Granted

Method for calculating phase shift coefficients of an M sequence

AssigneeFujitsu Limited

InventorsTakaharu Nakamura, Kazuo Kawabata, Kazuhisa Ohbuchi

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Abstract

An n-bit binary value corresponding to an amount of phase shift d is assigned to an SREG, and a shift operation is performed. An n-bit vector value corresponding to a decimal value “1” is assigned to an LAT as an initial value. Thereafter, the input from an SW is sequentially stored. An MUL performs a square operation within a Galois field GF (2n) for the output of the LAT. A DBL performs a double operation within the Galois field GF (2n) for the output of the MUL. The SW selects either of the outputs of the MUL and the DBL according to the output value from the MSB side of the SREG. After the shift operation and the latch operation are performed a number of times n, the n-bit output of the LAT is output as respective phase shift coefficients b0 through bn−1.

Claims6

Dependent claims

An M sequence phase shift coefficient calculating method for calculating respective phase shift coefficients b0 through bn−1 intended for obtaining an M sequence xdai whose phase is shifted by d bits from an output ai of an M sequence generated by a primitive polynomial f(x) of n degrees by using a linear combination of respective M sequences x0ai through xn−1ai, whose phases are shifted by 0 to n−1 bits from the output ai, comprising:

a first step of inputting a binary value of an amount of phase shift d;
a second step of setting an n-bit vector value, which corresponds to a decimal value “1”, as an initial input vector value;
a third step of setting a target bit as a most significant bit of a binary value of the amount of phase shift d input in said first step;
a fourth step of multiplying an input vector value with a vector value of a primitive element α within a Galois field GF (2n) and using a multiplication result as an output vector value if the target bit is “1”, and of defining the input vector value as an unchanged output vector value if the target bit is “0”;
a fifth step of performing a square operation within the Galois field GF (2n) for the output vector value obtained in said fourth step;
a sixth step of shifting a position of the target bit to a least significant bit side by 1 bit in the binary value of the amount of phase shift d, which is input in said first step, and of performing said fourth and fifth steps by using a result of the square operation performed in said fifth step as a newly input vector value;
and
a seventh step of outputting respective elements of operation results which are obtained so far as the respective phase shift coefficients b0 through bn−1, when said fourth and fifth steps has been performed for all of bits structuring the binary value of the amount of phase shift d input in said first step.

5 more elements

An M sequence phase shift coefficient calculating device for calculating respective phase shift coefficients b0 through bn−1 intended for obtaining an M sequence xdai whose phases is shifted by d bits from an output ai of an M sequence generated by a primitive polynomial f(x) of n degrees by using a linear combination of respective M sequences x0ai through xn−1ai, whose phases are shifted by 0 to n−1 bits from the output ai, comprising:

an n-stage shift register circuits to which an n-bit binary value corresponding to an amount of phase shift d is assigned, for performing a shift operation in synchronization with a clock, and outputting a most significant bit side output as a switch control signal;
a latch circuit, to which an n-bit vector value corresponding to a decimal value “1” is assigned as an initial vector value, for thereafter sequentially holding an n-bit input in synchronization with the clock;
a square operation circuit for performing a square operation within a Galois field GF (2n) for an n-bit output of said latch circuit;
a double operation circuit for performing a double operation within the Galois field GF (2n) for an n-bit output of said square operation circuit;
and
a switch circuit for selecting either of the n-bit output of said square operation circuit and the n-bit output of said double operation circuit according to the switch control signal, and for outputting a selected output to said latch circuit, wherein the n-bit output of said latch circuit is output, as the respective phase shift coefficients b0 through bn−1 after a shift operation and a latch operation are performed a number of times n.

3 more elements

Dependencies are inferred from the claim text.