Synchronizing source-synchronous links in a switching device

A method for synchronizing components operating isochronously that are coupled by independent links comprising:

• providing a synchronization signal from a first component to a plurality of second components through independent first links;
• upon detection of the synchronization signal at a respective second component, returning an acknowledgment signal from each of the second components to the first component through one of a like plurality of second links;
• when all the acknowledgment signals have been returned, terminating the transmission of the synchronization signal from the first component to the plurality of second components;
• upon detecting the termination of the synchronization signal at each second component, initializing data transfer on the second links.

A method of synchronizing a plurality of components, comprising:

• transmitting an initialization signal to each of the plurality of components via a corresponding plurality of independent links;
• receiving acknowledgment signals from respective ones of the plurality of components;
• and
• concurrently terminating transmission of the initialization signals to the plurality of components in response to receiving a last one of the acknowledgement signals.

A circuit for synchronizing a plurality of components, comprising:

• first logic configured to transmit an initialization signal to each of the plurality of components;
• second logic configured to receive acknowledgement signals from respective ones of the plurality of components;
• third logic configured to terminate transmission of the initialization signals to the plurality of components in response to receiving a last one of the acknowledgement signals;
• a buffer for storing received packets after transmission of the initialization signals is terminated;
• a trigger circuit for generating a trigger signal when a first packet is received;
• and
• read logic for reading packets from the buffer a predetermined time after the trigger signal is generated.

A circuit for synchronizing the transfer of packets from a plurality of components, comprising:

• a memory for storing packets transferred from the plurality of components;
• a trigger circuit for generating a trigger signal only when a first packet of the packets from the plurality of components is received;
• and
• read logic for reading packets from the memory a predetermined time after the trigger signal is generated.