Semiconductor memory device having write latency operation and method thereof

A method for controlling a write latency operation of a semiconductor memory device, comprising the steps of:

• delaying an address by n+m clock cycles in response to a clock signal;
• generating a first control signal by combining a column address strobe (CAS) latency signal of n-value and a first operation signal, when the n-value of the CAS latency is less than a predetermined value and write latency is fixed;
• generating a second control signal by combining the column address strobe (CAS) latency of n-value and a second operation signal, when the n-value of the CAS latency is equal to or greater than the predetermined value and the write latency is variable;
• and
• outputting the address delayed by the n+m clock cycles in response to a corresponding one of the first and second control signal.

A semiconductor memory device, comprising:

• an address shifting circuit for shifting an address by a predetermined number of clock cycles to generate a plurality of delayed addresses, in response to a clock signal;
• a control signal generating circuit for combining column address strobe (CAS) latency and one of first and second operation signals based on a value of the CAS latency to generate a control signal;
• and
• a switching circuit for selecting one of the delayed addresses output from the address shifting circuit in response to the control signal.

A method for controlling a write latency operation of a semiconductor memory device, comprising the steps of:

• shifting an address by a predetermined number of clock cycles to generate a plurality of delayed addresses, in response to a clock signal;
• generating a control signal by combining column address strobe (CAS) latency and one of first and second operation signals based on a value of the CAS latency;
• and
• selecting one of the delayed addresses in response to the control signal.