Fast cycle ram having improved data write operation

A semiconductor memory device comprising:

• a memory core section;
• an address register provided in said memory core section, for latching an address of a memory cell which is a to-be-written object;
• data registers provided in said memory core section, each for latching data to be written into the memory cell;
• DQ write drivers arranged in said memory core section, each for driving a corresponding one of data line pairs according to write data latched in said data register;
• DQ read amplifiers provided in correspondence to said DQ write drivers in said memory core section, each for amplifying readout data read out on the data line pair;
• a coherency detector for determining whether or not an input address coincides with an address which is held in said address register and in which the data write operation into the memory cell is not yet actually completed;
• and
• a switching circuit for selectively supplying one of readout data amplified by said DQ read amplifier and data latched in said data register to a readout data line in response to an output signal of said coherency detector;
• wherein the operation for writing data latched in said data register into the memory cell in response to input of a write command is started in response to input of a write command in a next clock cycle, a sense operation of data on the data line pair is interrupted when a read command is input before the next write command and coincidence of the address is detected in said coherency detector, and then, data latched in said data register is selected instead of the amplification result of said DQ read amplifier by use of said switching circuit, transferred to a readout data line pair and output to the exterior.

A fast cycle random access memory comprising:

• a clock buffer supplied with a clock signal used as a reference of an operation timing from the exterior;
• a command decoder & controller supplied with a control signal and command, for decoding the command and controlling the operations of circuits based on the result of decoding and the control signal;
• an address buffer supplied with an address signal, for outputting a row address signal and column address signal in response to the clock signal supplied from said clock buffer;
• an address register connected to said address buffer, for holding address information of a memory cell subjected to a late write operation;
• a memory cell array having memory cells arranged therein;
• a row decoder for decoding a row address signal supplied from said address buffer to select a row of a memory cell in said memory cell array;
• a column decoder for decoding a column address signal supplied from said address buffer to specify a column of a memory cell in said memory cell array;
• a sense amplifier and I/O gate for sensing and amplifying data to be written into the memory cell or data read out from the memory cell and then transferring the data;
• an I/O control circuit for controlling input/output of data;
• a data input buffer to which write data input to a data pin is input, the write data input to said data input buffer being supplied to a selected one of the memory cells in said memory cell array via said I/O control circuit and said sense amplifier & I/O gate;
• an input data register connected to said data input buffer, for holding write data information of a memory cell subjected to the late write operation;
• a data output buffer to which readout data from a selected one of the memory cells in said memory cell array is supplied via said sense amplifier & I/O gate and said I/O control circuit, said data output buffer outputting readout data from the data pin;
• and
• a control signal generator supplied with an output signal of said clock buffer and an output signal of said command decoder & controller, for generating control signals for controlling said row decoder, column decoder, input data register, I/O control circuit, data input buffer and data output buffer;
• wherein said memory cell array, address register, row decoder, column decoder, sense amplifier & I/O gate and I/O control circuit are arranged in a memory core section and said clock buffer, command decoder & controller, address buffer, control signal generator, data input buffer and data output buffer are arranged in a peripheral area of the memory core section.

A data write method for a fast cycle random access memory comprising the steps of:

• supplying a write command used as a first command and a column address latch command used as a second command as one packet;
• fetching the write command and column address latch command is synchronism with two successive clock signals;
• generating a write gate pulse in response to input of the write command to activate a DQ write driver and drive a data line pair according to the contents of an internal node of an input data register;
• and
• selecting a column selection line in response to input of the column address latch command, turning ON and I/O gate to transfer data line pair to a bit line pair and writing the data into a memory cell.