Semiconductor memory device having row buffers
AssigneeHynix Semiconductor Inc.
InventorByung Joo Kang
Life of this patent
Estimating the term…
Abstract
A semiconductor memory device has, among other things, a row buffer. The semiconductor memory device includes a memory cell array for storing data, the row buffer for storing data of a row of the memory cell array, and a state machine for controlling the semiconductor memory device. The semiconductor memory device stores data of the row determined by an inputted address signal from the memory cell array in the row buffer when a predetermined external command is inputted from the external, and outputs a part of the data according to the address signal from the row buffer to the external in a predetermined delay time.
Claims16
A semiconductor memory device having a row buffer and being compatible with a SRAM, the semiconductor memory device comprising:
- a memory cell array for storing data;
- the row buffer for storing data of a row of the memory cell array;
- and
- a state machine for controlling the semiconductor memory device to firstly store data of the row determined by an inputted address signal from the memory cell array in the row buffer when a single predetermined external command is inputted from the external, and then to output a part of the data according to the address signal from the row buffer to the external in a predetermined delay time, wherein the part of the data are outputted to the external through the row buffer by one predetermined external command.
A semiconductor memory device, comprising:
- a memory cell array for storing data;
- a row buffer for storing data of a row of the memory cell array;
- and
- a state machine for controlling the semiconductor memory device to firstly store data of the row determined by an inputted address signal from the memory cell array in the row buffer when a predetermined external command is inputted from the external, and then to output a part of the data according to the address signal from the row buffer to the external in a predetermined delay time, wherein the state machine comprises:
- a command decoder for generating column activation signal, mode register set signal and first internal command signal;
- a mode decoder for generating mode signals determining the generation time of column activation signal according to corresponding address signal when the mode register set signal is inputted from the command decoder;
- and
- a control block for generating control signal which controls the command decoder to generate the column activation signal at the time determined by the mode signals when the first internal command signal is inputted from the command decoder according to the input of the predetermined external command.
The semiconductor memory device having a memory cell array for storing data and a row buffer for storing data of a row of the memory cell array, comprising:
- a command decoder for generating column activation signal, mode register set signal and first internal command signal;
- a mode decoder for generating mode signals determining the generation time of column activation signal according to corresponding address signal when the mode register set signal is inputted from the command decoder;
- a control block for generating control signal which controls the command decoder to generate the column activation signal at the time determined by the mode signals when the first internal command signal is inputted from the command decoder according to the input of the predetermined external command;
- an address latch unit for latching address signal inputted from the external;
- and
- a clock buffer unit for generating a first internal clock signal for synchronizing the command decoder and a second internal clock signal for synchronizing the address latch unit by receiving an external clock signal and the control signal.
A method of controlling the semiconductor memory device having a row buffer and being compatible with a SRAM, the method comprising steps of:
- storing data of a row of a memory cell array in the row buffer according to address signal when a single predetermined external command is inputted from the external;
- and
- outputting a part of the data determined by the address signal from the row buffer to the external without any additional command from the external, after a predetermined delay time from the step of storing data in the row buffer, wherein the part of the data are outputted to the external through the row buffer by one predetermined external command.
A method of controlling the semiconductor memory device having a row buffer comprising steps of:
- storing data of a row of a memory cell array in the row buffer according to address signal when a predetermined external command is inputted from the external, wherein the step of storing data in the row buffer is performed by:
- selecting a row of the memory cell array according to address signal when the row activation signal is outputted from the command decoder unit according to the input of the predetermined external command;
- and
- storing data of the selected row in the row buffer through a bit line sense amp;
- and
- outputting a part of the data determined by the address signal from the row buffer to the external without any additional command from the external, after a predetermined delay time from the step of storing data in the row buffer.
Dependencies are inferred from the claim text.