Non-volatile memory element having a cascoded transistor scheme to reduce oxide field stress

A memory cell comprising:

• a first select transistor having a source-drain path and a gate;
• a second select transistor having a source-drain path connected in series with the source-drain path of the first select transistor, and having a gate;
• a floating gate storage transistor having a source-drain path connected in series with the source-drain path of the second select transistor;
• a means for applying a voltage to the gate of the first select transistor so that when a bitline programming voltage is applied to the source-drain path of the first select transistor to enable programming of the floating gate storage transistor, and when programming of the floating gate storage transistor is not desired, damage will not occur to an oxide material between the gate and drain of the first select transistor;
• and
• a means for applying a voltage to the gate of the second select transistor so that when the bitline programming voltage is applied to the source-drain path of the first select transistor, and programming of the floating gate storage transistor is not desired, charge stored by the floating gate storage transistor will not be disturbed.

A memory cell comprising:

• a first select transistor having a source-drain path and a gate;
• a second select transistor having a source-drain path connected in series with the source-drain path of the first select transistor, and having a gate;
• a floating gate storage transistor having a source-drain path connected in series with the source-drain path of the second select transistor;
• a first voltage reference configured for providing a voltage to the gate of the first select transistor so that when a bitline programming voltage is applied to the source-drain path of the first select transistor to enable programming of the floating gate storage transistor, and when programming of the floating gate storage transistor is not desired, damage will not occur to an oxide material between the gate and drain of the first select transistor;
• and
• a second voltage reference configured for providing a voltage to the gate of the second select transistor so that when the bitline programming voltage is applied to the source-drain path of the first select transistor, and programming of the floating gate storage transistor is not desired, charge stored by the floating gate storage transistor will not be disturbed.

An array of memory cell transistors comprising:

• memory cells comprising:
• a first select transistor having a source-drain path and a gate;
• a second select transistor having a source-drain path connected in series with the source-drain path of the first select transistor, and having a gate;
• and
• a floating gate storage transistor having a source-drain path connected in series with the source-drain path of the second select transistor;
• a first array output connected to the source-drain path of the floating gate storage transistor in a first portion of the memory cells;
• and
• a second array output connected to the source-drain path of the floating gate storage transistor in a second portion of the memory cells.

A memory cell comprising:

• a first select transistor having a source-drain path and a gate;
• a second select transistor having a source-drain path in series with the source-drain path of the first select transistor, and having a gate;
• a floating gate transistor having a source-drain path connected in series with the source-drain path of the second select transistor;
• an output line connected to the source-drain path of the floating gate transistor;
• and
• a bitline connected to the source-drain path of the first select transistor.