Semiconductor memory device including non-volatile memory cell array having MOS structure in well region formed on semiconductor substrate

A semiconductor memory device comprising:

• a semiconductor substrate of a first conductive type;
• a first well region of a second conductive type formed on the semiconductor substrate;
• a second well region of a first conductive type formed in the first well region;
• a memory cell array in which memory cells with a MOS structure are arranged in a matrix manner in the second well region;
• a first decoding circuit for selectively applying a rewriting voltage signal to the second well region and a source region of the memory cell at the time of rewriting data in the memory cell array;
• a second decoding circuit configured to decode address signals supplied to the semiconductor memory device for selectively applying the rewriting voltage signal to the first well region;
• wherein the first well region, the second well region, the first decoding circuit and the second decoding circuit constitute one rewriting block, a plurality of data rewriting blocks are continuously arranged to each other to constitute a rewriting block group, and the rewriting voltage signal is supplied to all the rewriting blocks in the same rewriting block group.