Fast program to program verify method
AssigneeHalo LSI, Inc.
InventorsSeiki Ogura, Tomoko Ogura, Nori Ogura
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Abstract
In the present invention a new method for program and program verify is described. The threshold voltage of the memory cell is shifted up and then measured with minimal charging and discharging of the bit lines and control gate lines. Bit line to control gate line capacitance is also used to reduce the number of voltage references needed. Program current is reduced by use of a load device coupled to the source diffusion. The result is increased program bandwidth with lower high voltage charge pump current consumption.
Claims5
A method of programming a dual storage site MONOS memory cell using bit line capacitance to provide charge during CHE programming, comprising:
- a) biasing a first control gate located above an unselected storage site of a MONOS memory cell to a first high voltage,
- b) biasing a second control gate located above a selected storage site of said memory cell to a second high voltage,
- c) biasing a first diffusion below said first control gate to zero volts,
- d) biasing a second diffusion below said second control gate to a third high voltage
- e) biasing a word gate of said memory cell to zero volts, then
- f) floating said first and second control gates and said first and second diffusions, then
- g) increasing said word gate voltage to a predetermined value, then
- h) programming said selected storage site with a flow of electrons between said first and second diffusions.
Dependencies are inferred from the claim text.