Control gate decoder for twin MONOS memory with two bit erase capability
AssigneeHalo LSI, Inc.
InventorsTomoko Ogura, Nori Ogura
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Abstract
The present invention is a decoder for control gate lines of a twin MONOS flash memory array. Decoder units connected to each control gate line of the memory are controlled to provide select, override and unselect voltages to perform read, program and erase operations. The decoder units are divided into odd and even addressing where separate voltages can be applied control gates of to adjacent memory cells. Override voltages, which prevent operations of a selected cell from affecting adjacent memory cell storage sites, can be applied to the control gates of immediate neighboring cells of the selected sell. Unselected voltages can be applied to beyond the immediate neighboring cells to further prevent disturb conditions in remote cells.
Claims27
A method for selecting a storage site within a twin MONOS flash memory for reading and programming using control gate override selection, comprising:
- a) selecting a first memory cell containing a first and a second storage site,
- b) selecting said first storage site within said first memory cell,
- c) selecting a first control gate above said first storage site,
- d) applying a “selected” voltage to said first control gate,
- e) selecting a second control gate above an unselected storage site within a second memory cell which is immediately adjacent to said first storage site,
- f) applying an “override” voltage to said second control gate,
- g) selecting a third control gate within a third memory cell which is above a second unselected cell and is not immediately adjacent to said first storage site,
- h) applying an “unselected” voltage to said third control gate.
A method for selecting a storage site within a twin MONOS flash memory for reading and programming using bit line override selection, comprising:
- a) selecting a first memory cell containing a first and a second storage site,
- b) selecting said first storage site within said first memory cell,
- c) selecting a first control gate above said first storage site,
- d) applying a “selected” voltage to said first control gate,
- e) selecting a second control gate above an unselected storage site within a second memory cell which is immediately adjacent to either side of said first memory cell,
- f) applying an “override” voltage to a second control gate,
- g) selecting a third control gate within a third memory cell which is not immediately adjacent to said first memory cell,
- h) applying an “unselected” voltage to said third control gate.
A control gate line decoder for an array containing twin MONOS flash memory cells, comprising:
- a) a decoder for control gate lines of a memory array,
- b) said control gate lines connected to a plurality of twin MONOS memory cells within said memory array,
- c) said decoder containing a plurality of decoder units connected to a plurality of said control lines,
- d) said plurality of decoder units divided into a plurality of odd and a plurality of even assigned addresses matching address of said memory cells,
- e) said plurality of odd assigned address decoder units connecting a low voltage or an odd assigned voltage to control gate lines with odd assigned addresses,
- f) said plurality of even assigned address decoder units connecting said low voltage or an even assigned voltage to control gate lines with even assigned addresses.
A means for decoding control gate signals for a twin MONOS flash memory, comprising:
- a) a first decoding means to select a first voltage from a first plurality of voltages to connect to a first control gate line,
- b) a second decoding means to select a second voltage from a second plurality of voltages to connect to a second control gate line,
- c) a third decoding means to select a third voltage from said first plurality of voltages or from said second plurality of voltages to connect to a third control gate line,
- d) a first addressing means to assign said first plurality of voltages to even addressed control lines,
- e) a second addressing means to assign said second plurality of voltages to odd addressed control lines.
Dependencies are inferred from the claim text.