Isolation of memory cells in cross point arrays
AssigneeHewlett-Packard Development Company, L.P.
InventorFrederick A. Perner
Life of this patent
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Abstract
A memory array includes memory cells located at cross points of first and second conductors. The memory cells are compound structures including an isolation element for isolating a memory cell from sneak path currents, and a re-writeable storage element for storing a binary state of the memory cell. The isolation elements include tunnel gate surface effect transistor gate oxides, and pillar diode structures. A control gate of the transistor disconnects the tunnel junction from sidewalls of the pillar, preventing sneak path current flow through the memory cells. The isolation elements in the memory cells do not require additional space on the substrate, allowing for a high array density. In addition, the memory cells have a low forward voltage drop, improving the readability of the memory array.
Claims16
A memory cell, comprising:
- an isolation element, comprising:
- a P− region;
- an N+ region surrounding the P− region, the P− region and the N+ region forming a pillar;
- and
- a gate oxide disposed at one end of the pillar;
- and
- a re-writeable storage element in series with the isolation element.
A memory array, comprising:
- a substrate;
- a plurality of first conductors disposed on the substrate;
- a plurality of second conductors, the plurality of second conductors crossing the first conductors at a plurality of cross points;
- and
- a plurality of memory cells, wherein each memory cell is disposed between a first conductor and a second conductor at a cross point, and wherein a memory cell comprises:
- an isolation element, comprising:
- a P− region;
- an N+ region surrounding the P− region, the P− region and the N+ region forming a pillar;
- and
- a gate oxide disposed at one end of the pillar;
- and
- a re-writeable storage element in series with the isolation element.
Dependencies are inferred from the claim text.