Graphics processing system with logic enhanced memory and method therefore

A video graphics processing circuit comprising:

• a graphics processing pipeline, wherein the graphics processing pipeline receives video graphics primitives and generates pixel fragments;
• a logic enhanced memory controller operably coupled to the graphics processing pipeline, wherein the logic enhanced memory circuit receives the pixel fragments generated by the graphics processing pipeline, wherein the logic enhanced memory circuit includes:
• a packing block that packs the pixel fragments into fragment blocks, wherein each of the fragment blocks includes at least one flit of valid data;
• and
• a control block that generates commands, wherein the control block issues the commands such that at least a portion of the commands are issued along with a corresponding fragment block, wherein the control block controls the issuance of commands such that an expected command processing rate is not exceeded based on monitoring of a number of flits included in fragment blocks accompanying issued commands.

A method for controlling issuance of memory commands to a logic enhanced memory circuit over a bus of limited bandwidth, comprising:

• receiving a memory command;
• determining if space is available in an input buffer of the logic enhanced memory circuit for the memory command, wherein such determination is made based on an expected processing speed of the logic enhanced memory circuit and historical data that corresponds to an expected transfer speed of previously issued memory commands across the bus;
• when space is available in the input buffer:
• issuing the memory command to the logic enhanced memory circuit;
• and
• updating the historical data.

A method for controlling issuance of memory commands to a logic enhanced memory circuit over a first bus of limited bandwidth, comprising:

• receiving a memory command;
• determining if space is available in an input buffer of the logic enhanced memory circuit for the memory command, wherein such determination is made based on an expected processing speed of the logic enhanced memory circuit and a first set of historical data that corresponds to an expected transfer speed of previously issued memory commands across the first bus;
• when space is available in the input buffer:
• determining if the memory command results in the production of output data by the logic enhanced memory circuit that is to be received over a second bus;
• when the memory command does not result in the production of output data by the logic enhanced memory circuit:
• issuing the memory command to the logic enhanced memory circuit;
• and
• updating the first set of historical data;
• when the memory command results in the production of output data by the logic enhanced memory circuit:
• determining if space is available in an output buffer of the logic enhanced memory circuit for the output data produce by the memory command, wherein such determination is made based on a second set of historical data that includes output data generation characteristics of the previously issued memory commands;
• when space is available in the output buffer:
• issuing the memory command to the logic enhanced memory circuit;
• and
• updating the second set of historical data.