Parallel communication based on balanced data-bit encoding

#The present invention is directed generally to data communication. More particularly, the present invention relates to methods and arrangements for transferring data over parallel data circuits and to encoding and decoding schemes for achieving relatively error-free data transfers between nodes.

#The electronics industry continues to strive for high-powered, high-functioning circuits. Significant achievements in this regard have been realized through the fabrication of very large-scale integration of circuits on small areas of silicon wafer. These complex circuits are often designed as functionally-defined modules that operate on a set of data and then pass that data on for further processing. This communication from such functionally-defined modules can be passed in small or large amounts of data between individual discrete circuits, between integrated circuits within the same chip, and between remotely-located circuits coupled to or within various parts of a system or subsystem. Regardless of the configuration, the communication typically requires closely-controlled interfaces to insure that data integrity is maintained and that circuit designs are sensitive to practicable limitations in terms of implementation space and available operating power.

#The demand for high-powered, high-functioning semiconductor devices has lead to an ever-increasing demand for accelerating the speed at which data is passed between the circuit blocks. Many of these high-speed communication applications can be implemented using parallel data transmission in which multiple data bits are simultaneously sent across parallel communication paths. Such “parallel bussing” is a well-accepted approach for achieving data transfers at high data rates. For a given data-transmission rate (sometimes established by a clock passed along with the data), the bandwidth, measured in bits-per-second, is equivalent to the data transmission rate times the number of data signals comprising the parallel data interconnect.

#The invention may be more completely understood in consideration of the following detailed description of various embodiments of the invention in connection with the accompanying drawings, in which:

#FIG. 1a is a diagram of a data-transmitting module with its I/O pads connected to a parallel-data communication line arrangement, that includes a processor with encoding methodology according to the present invention;

#FIG. 1b is a voltage plot of the internal Vdd and Vss signals in response to a transmission on the parallel data communication arrangement side of the I/O pads, corresponding to an unbalanced data transmission, for example, as could be implemented by the data-transmitting module shown FIG. 1a;

#While the invention is amenable to various modifications and alternative forms, specifics thereof have been shown by way of example in the drawings and will be described in detail. It should be understood, however, that the intention is not to limit the invention to the particular embodiments described. On the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.

#The present invention is believed to be generally applicable to methods and arrangements for transferring data between two modules (functional blocks) intercoupled by a parallel data communication path. The invention has been found to be particularly advantageous for high-speed data transfer applications requiring or benefiting from preservation of data integrity and reductions in implementation space and power consumption. Examples of such applications include, among others, SSTL (stub series transceiver logic), RSL (Rambus Signaling Logic) interfaces, closely-connected applications such as where the parallel data communication path intercouples the two modules on a single-chip, off-board high-speed communication between chips immediately adjacent to each other on the same printed circuit board such as on a reference-chip development platform of the type disclosed in U.S. patent application Ser. No. 09/215,942, filed on Dec. 18, 1998, now U.S. Pat. No. 6,347,395. While the present invention is not necessarily limited to such applications, an appreciation of various aspects of the invention is best gained through a discussion of examples in such an environment.

#According to one example embodiment of the present invention, a parallel data communication arrangement passes digital data at a rate set by clock signals that are carried along with the data lines of the parallel data bus. The arrangement further includes an interface circuit adapted to encode onto the parallel data lines a set of X bits of the digital data as an encoded set of Y bits, where Y is greater than X. For example, in one application X is 4 and Y is 8, and in another application X is 8 and Y is 10. The encoding is performed by converting the data set of X bits into the set of Y bits with a bias toward balancing the quantity of ones and zeroes in the set of encoded bits. By improving the balance between the quantity of ones and zeroes, the implementation can be used to reduce the current flow between transmitting and receiving modules and thereby reduce EMI, reduce the number of power pins (or, more generally, power nodes) required for the interconnect interface, and/or reduce the I/O delay and the skew in the signals passed over the parallel data bus.