Decimated digital phase-locked loop for high-speed implementation
AssigneeTexas Instruments Incorporated
InventorsBhavesh G. Bhakta, Younggyun Kim
Life of this patent
Estimating the term…
Abstract
A phase lock loop to control phase error from a first input signal and a second input signal including a phase error detector to detect a phase error signal between the first input signal and the second input signal at a predetermined rate, a down-sampling circuit to down-sample the phase error signal and to output a down-sampled signal at a reduced rate with respect to the predetermined rate, a loop filter to filter the down-sampled signal to obtain a filtered signal, and an up-sampling circuit to up-sample the filtered signal at the predetermined rate.
Claims4
A phase lock loop to control phase error from a first input signal and a second input signal, comprising
- a phase error detector to detect a phase error signal between said first input signal and said second input signal at a predetermined rate;
- a down-sampling circuit to down-sample said phase error signal and to output a down-sampled signal at a reduced rate with respect to said predetermined rate;
- a loop filter to filter said down-sampled signal to a filtered signal;
- and
- an up-sampling circuit to up-sample said filtered signal at said predetermined rate.
Dependencies are inferred from the claim text.