Compact cascode radio frequency CMOS power amplifier
AssigneeKoninklijke Philips Electronics N.V.
InventorVickram Vathulya
Life of this patent
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Abstract
An integrated circuit chip includes a cascode amplifier having a first NMOS transistor with the gate receiving an input signal a source connected to ground through an inductance and a drain connected to the source of a second NMOS transistor. The drain of the second transistor is connected to a supply voltage through another inductance. The gate of the second transistor is connected to a DC bias voltage through a resistor and is connected to a first plate of an on-chip parallel plate capacitor. The other plate of the capacitor is connected to a wirebond pad for connection to a circuit board through a bond wire. The capacitor together with the inductance of the bond wire form a short circuit at the operating voltage of the amplifier.
Claims10
An integrated circuit chip, comprising:
- an input signal path;
- an amplified output signal path;
- a DC bias voltage path;
- a reference voltage path;
- a ground path;
- a radio frequency cascode power amplifier, including:
- one or more on-chip parallel-plate capacitors, each capacitor having a first plate connected to a different respective interconnect terminal for communication through an inductive element to a ground path on a circuit board and each capacitor having a second plate;
- a first transistor with a first transistor control terminal controlling the current between a first transistor first terminal and a first transistor second terminal with the first transistor first terminal connected to the ground path and the first transistor control terminal connected to the input signal path for receiving a radio frequency input signal;
- and
- a second transistor with a second transistor control terminal controlling the current between a second transistor first terminal and a second transistor second terminal with the second transistor first terminal connected to the first transistor second terminal, the second transistor second terminal connected to the amplified output signal path and connected to the reference voltage path through a pull-up inductor, and the second transistor control terminal connected to the second plates of the on-chip parallel-plate capacitors and connected to the bias voltage path through a current limiting element.
A circuit board assembly comprising:
- a circuit board;
- a ground path of the circuit board connected to a first interconnect terminal and a third interconnect terminal of the circuit board;
- a reference voltage path of the circuit board connected to a second interconnect terminal of the circuit board;
- and
- an integrated circuit chip mounted on the circuit board and including:
- an input signal path;
- an amplified output path;
- a ground path of the chip connected to a first interconnect terminal on the chip surface;
- a reference voltage path of the chip connected to a second interconnect terminal on the chip surface;
- a DC bias voltage path;
- one or more on-chip parallel-plate capacitors, each capacitor having a first plate connected to a different third interconnect terminal on the surface of the chip and each capacitor having a second plate;
- a first transistor with a first transistor control terminal controlling the current between a first transistor first terminal and a first transistor second terminal, with the first transistor first terminal connected to the ground path of the chip and the first transistor control terminal connected to the input signal path for receiving a radio frequency input signal;
- a second transistor with a second transistor control terminal controlling the current between a second transistor first terminal and a second transistor second terminal with the second transistor first terminal connected to the first transistor second terminal, the second transistor second terminal connected to the amplified signal output path and to the reference voltage path through a pull-up inductor, and the second transistor control terminal connected to the second plate of each on-chip parallel-plate capacitor and to the bias voltage path;
- and
- a current limiting element through which the bias voltage path is connected to the control terminal of the second transistor;
- the assembly further comprising:
- a first conductor connecting between the first interconnect terminal of the circuit board surface and the first interconnect terminal on the chip surface for providing the ground potential to the chip;
- a second conductor connecting between the second interconnect terminal of the circuit board surface and the second interconnect terminal on the chip surface for providing the reference potential to the chip;
- and
- one or more third conductors each connecting between a corresponding one of the third interconnect terminals of the circuit board surface and a corresponding one of the third interconnect terminals on the chip surface;
- and wherein a respective inductive element is connected between each first plate of a corresponding on-chip parallel plate capacitor and the ground path of the circuit board.
An integrated circuit chip, comprising:
- an input signal path;
- an amplified output signal path;
- a DC bias voltage path;
- a reference voltage path;
- a ground path;
- a radio frequency cascade power amplifier, including:
- one or more on-chip parallel-plate capacitors, each capacitor having a first plate communicating with a different respective interconnect terminal for communication through an inductive element to a ground path on a circuit board and each capacitor having a second plate;
- a first transistor with a first transistor control terminal controlling the current between a first transistor first terminal and a first transistor second terminal with the first transistor first terminal communicating with the ground path and the first transistor control terminal communicating with the input signal path for receiving a radio frequency input signal;
- and
- a second transistor with a second transistor control terminal controlling the current between a second transistor first terminal and a second transistor second terminal with the second transistor first terminal communicating with the first transistor second terminal, the second transistor second terminal also communicating with the amplified output signal path and communicating with the reference voltage path through a pull-up inductor, and the second transistor control terminal communicating with the second plates of the on-chip parallel-plate capacitors and communicating with the bias voltage path through a current limiting element.
A circuit board assembly comprising:
- a circuit board;
- a ground path of the circuit board;
- a reference voltage path of the circuit board;
- and
- an integrated circuit chip mounted on the circuit board and including:
- an input signal path;
- an amplified output signal path;
- a ground path of the chip communicating with the ground path of the circuit board;
- a reference voltage path of the chip communicating with the reference voltage path of the circuit board;
- a DC bias voltage path;
- one or more on-chip parallel-plate capacitors, each capacitor having a first plate communicating with the ground path of the circuit board and each capacitor having a second plate;
- a first transistor with a first transistor control terminal controlling the current between a first transistor first terminal and a first transistor second terminal with the first transistor first terminal communicating with the ground path and the first transistor control terminal communicating with the input signal path for receiving a radio frequency input signal;
- a second transistor with a second transistor control terminal controlling the current between a second transistor first terminal and a second transistor second terminal with the second transistor first terminal communicating with the first transistor second terminal, the second transistor second terminal communicating with the amplified signal output path and with the reference voltage path through a pull-up inductor, and the second transistor control terminal communicating with the second plate of each on-chip parallel-plate capacitor;
- and
- a current limiting element connected in the communication between the bias voltage path and the second transistor control terminal;
- and wherein a responsive inductive element is connected in the communication between the first plate of each on-chip parallel plate capacitor and the ground path of the circuit board.
Dependencies are inferred from the claim text.