Input/output buffer incorporating filter for powerline communications line
AssigneeEchelon Corporation
InventorsPhilip H. Sutterlin, Walter J. Downey
Life of this patent
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Abstract
An improvement in a buffer for driving a signal onto a power line is described. The buffer includes a second order filter. With the improvement, the collector-to-emitter potential of an emitter follower is maintained constant to substantially reduce the distortion associated with base-collector capacitance.
Claims18
A method for reducing distortion in an emitter follower circuit where an input signal is coupled through resistance, comprising:
- maintaining substantially constant a collector-to-emitter potential of a transistor in the emitter follower circuit in such a way that the output swing of the circuit is not degraded;
- and
- applying the input signal to the emitter follower circuit.
An emitter follower circuit including:
- an input signal source for the circuit having resistance;
- and
- means for maintaining the collector-to-emitter potential of a first transistor substantially constant such that the input signal can drive an output signal where the means for maintaining the collector-to-emitter potential of the first transistor does not degrade how close to a power supply rail the output signal may drive.
In an input/output buffer for transmitting a communication signal over a power line which can be turned off to produce a high impedance at its output and which includes a transmit filter and an output stage having a first pair of emitter followers for driving an output in a first direction and a second pair of emitter followers for driving the output in a second direction, an improvement comprising:
- a transistor coupled between an emitter of one of the pairs of emitter followers to a common node formed by a collector of the first pair of the emitter followers and a collector of the second pair of the emitter followers.
A buffer comprising:
- a filter;
- a first emitter follower pair comprising a first PNP transistor and a first NPN transistor;
- a second emitter follower pair comprising a second NPN transistor and a second PNP transistor;
- the base of the first PNP transistor and the base of the second NPN transistor being coupled to the filter;
- the collector of the first PNP transistor and the collector of the second NPN transistor being connected to a common node;
- a third NPN transistor having its base connected to the emitter of the first PNP transistor and its emitter connected to the common node.
A buffer comprising:
- a filter;
- a first emitter follower pair comprising a first PNP transistor and a first NPN transistor;
- a second emitter follower pair comprising a second NPN transistor and a second PNP transistor;
- the base of the first PNP transistor and the base of the second NPN transistor being coupled to the filter;
- the collector of the first PNP transistor and the collector of the second NPN transistor being connected to a first node;
- the emitter of the first NPN transistor and the emitter of the second PNP transistor being coupled to a second node;
- and
- the first and second nodes being connected.
Dependencies are inferred from the claim text.