Amplification circuit with constant output voltage range

An amplification circuit, comprising:

• a first MOS transistor having a gate to which a first input terminal for inputting a positive logic input signal is connected and a drain to which a first load is connected:
• a second MOS transistor having a gate to which a second input terminal for inputting a negative logic input signal, which composes differential input signals with the positive logic input signal, is connected and a drain to which an output terminal and a second load are connected, and pairing up with said first MOS transistor;
• and
• a current source to which sources of said first and second MOS transistors are connected, for supplying a constant current to the first and/or second load when a difference in voltages between the first and second input terminals is equal to or less than a predetermined positive threshold, and supplying a variable current to the first and/or second load when the difference in the voltages is greater than said predetermined positive threshold,
• wherein one end of each of the first and second loads is connected to the drains of said first and second MOS transistors respectively and the other end thereof is connected to a first potential via a third load,
• wherein one end of said current source is connected to the sources of said first and second MOS transistors and the other end thereof is connected to a second potential,
• wherein said first and second MOS transistors are n-channel MOS transistors, and
• wherein said current source supplies the variable current which causes a voltage of the output terminal to be constant when the difference in the voltages between the first and second input terminals is greater than the predetermined positive threshold.

An amplification circuit, comprising:

• a first MOS transistor having a gate to which a first input terminal for inputting a positive logic input signal is connected and a drain to which a first load is connected;
• a second MOS transistor having a gate to which a second input terminal for inputting a negative logic input signal, which composes differential input signals with the positive logic input signal, is connected and a drain to which an output terminal and a second load are connected, and pairing up with said first MOS transistor, and
• a current source to which sources of said first and second MOS transistors are connected, for supplying a constant current to the first and/or second load when a difference in voltages between the first and second input terminals is between predetermined negative and positive thresholds, and supplying a variable current to the first and/or second load when the difference in the voltages is smaller than said predetermined negative threshold or greater than said predetermined positive threshold,
• wherein one end of each of the first and second loads is connected to the drains of said first and second MOS transistors respectively and the other end thereof is connected to a first potential via a third load,
• wherein one end of said current source is connected to the sources of said first and second MOS transistors and the other end thereof is connected to a second potential,
• wherein said first and second MOS transistors are n-channel MOS transistors, and
• wherein, when the difference in the voltages between the first and second input terminals is smaller than said negative threshold or greater than said positive threshold, said current source supplies the variable current which causes an output voltage of the output terminal to be constant at first and second output voltage values, respectively.

An amplification circuit, comprising:

• a first MOS transistor having a gate to which a first input terminal for inputting a positive logic input signal is connected and a drain to which a first load is connected;
• a second MOS transistor having a gate to which a second input terminal for inputting a negative logic input signal, which composes differential input signals with the positive logic input signal, is connected and a drain to which an output terminal and a second load are connected, and pairing up with said first MOS transistor, and
• a current source to which sources of said first and second MOS transistors are connected, for supplying a constant current to the first and/or second load when a difference in voltages between the first and second input terminals is equal to or greater than a predetermined negative threshold, and supplying a variable current to the first and/or second load when the difference in the voltages is smaller than said predetermined negative threshold,
• wherein one end of each of the first and second loads is connected to the drains of said first and second MOS transistors respectively and the other end thereof is connected to a first potential via a third load or directly,
• wherein one end of said current source is connected to the sources of said first and second MOS transistors and the other end thereof is connected to a second potential,
• wherein said first and second MOS transistors are p-channel MOS transistors, and
• wherein said current source supplies the variable current which causes a voltage of the output terminal to be constant when the difference in the voltages between the first and second input terminals is smaller than said predetermined negative threshold.

An amplification circuit, comprising:

• a first MOS transistor having a gate to which a first input terminal for inputting a positive logic input signal is connected and a drain to which a first load is connected;
• a second MOS transistor having a gate to which a second input terminal for inputting a negative logic input signal, which composes differential input signals with the positive logic input signal, is connected and a drain to which an output terminal and a second load are connected, and pairing up with said first MOS transistor;
• and
• a current source to which sources of said first and second MOS transistors are connected, for supplying a constant current to the first and/or second load when a difference in voltages between the first and second input terminals is equal to or less than a predetermined positive threshold, and supplying a variable current to the first and/or second load when the difference in the voltages is greater than said predetermined positive threshold,
• wherein one end of each of the first and second loads is connected to the drains of said first and second MOS transistors respectively and the other end thereof is connected to a first potential via a third load,
• wherein one end of said current source is connected to the sources of said first and second MOS transistors and the other end thereof is connected to a second potential,
• wherein said first and second MOB transistors are p-channel MOS transistors, and
• wherein said current source supplies a current which causes a voltage of the output terminal to be constant when the difference in the voltages between the first and second input terminals is greater than said predetermined positive threshold.

An amplification circuit, comprising:

• a first MOS transistor having a gate to which a first input terminal for inputting a positive logic input signal is connected and a drain to which a first load is connected:
• a second MOS transistor having a gate to which a second input terminal for inputting a negative logic input signal, which composes differential input signals with the positive logic input signal, is connected and a drain to which an output terminal and a second load are connected, and pairing up with said first MOS transistor;
• and
• a current source to which sources of said first and second MOS transistors are connected, for supplying a constant current to the first and/or second load when a difference in voltages between the first and second input terminals is between predetermined negative and positive thresholds, and supplying a variable current to the first and/or second load when the difference in the voltages is smaller than said predetermined negative threshold or greater than said positive threshold,
• wherein one end of each of the first and second loads is connected to the drains of said first and second MOS transistors respectively and the other end thereof is connected to a first potential via a third load,
• wherein one end of said current source is connected to the sources of said first and second MOS transistors and the other end thereof is connected to a second potential,
• wherein said first end second MOS transistors are p-channel MOS transistors, and
• wherein, when the difference in the voltages between the first and second input terminals is greater than said positive threshold or smaller than said negative threshold, said current source supplies the variable current which causes an output voltage of the output terminal to be constant at first and second output voltage values, respectively.