Logarithmic amplifier with temperature compensated detection scheme

A voltage mode logarithmic amplifier for producing a decibel scaled output voltage signal, comprising:

• a first gain stage for providing at least one amplified rectified voltage signal responsive to at least one input voltage signal;
• a second gain stage for providing at least one further amplified rectified signal responsive to said at least one input voltage signal and said at least one amplified rectified signal;
• an output node for producing at least one output voltage signal that is responsive to said at least one amplified rectified voltage signal and said at least one further amplified rectified voltage signal;
• a self-biased replica stage operative to provide at least one voltage offset signal responsive to temperature;
• and
• at least one differential amplifier operative to receive said at least one voltage offset signal and provide a temperature corrected output voltage signal responsive to said at least one input voltage signal, wherein said at least one differential amplifier is communicatively coupled to both said first gain stage and said second gain stage.

A voltage mode logarithmic amplifier comprising:

• at least one first transistor device having a first base node, a first collector node and a first emitter node;
• at least one second transistor device having a second base node, a second collector node and a second emitter node, wherein said second emitter node is communicatively coupled with said first emitter node, and wherein said first and second transistor devices are configured to receive a voltage input signal such that said voltage input signal is applied across said first and second base nodes;
• at least one third transistor device having a third base node, a third collector node and a third emitter node, wherein said third base node is communicatively coupled to said second collector node;
• at least one fourth transistor device having a fourth base node;
• a fourth collector node and a fourth emitter node, wherein said fourth base node is communicatively coupled to said first collector node, and wherein said fourth emitter node is communicatively coupled to said third emitter node;
• and
• at least one raw output node configured to provide at least one raw output voltage signal responsive to said input voltage signal, wherein said raw output node is communicatively coupled to said first, second, third and fourth emitter nodes.

A voltage mode logarithmic amplifier comprising:

• at least one first transistor device having a first base node, a first collector node and a first emitter node;
• at least one second transistor device having a second base node, a second collector node and a second emitter node, wherein said second emitter node is communicatively coupled with said first emitter node, and wherein said first and second transistor devices are configured to receive a voltage input signal such that said voltage input signal is applied across said first and second base nodes;
• at least one third transistor device having a third base node, a third collector node and a third emitter node, wherein said third base node is communicatively coupled to said second collector node;
• at least one fourth transistor device having a fourth base node, a fourth collector node and a fourth emitter node, wherein said fourth base node is communicatively coupled to said first collector node, and wherein said fourth emitter node is communicatively coupled to said third emitter node;
• at least one raw output node configured to provide at least one raw output voltage signal responsive to said input voltage signal, wherein said raw output node is communicatively coupled to said first, second, third and fourth emitter nodes;
• at least one voltage offset correction circuit operative to provide a voltage offset responsive to temperature;
• and
• at least one differential amplifier circuit operative to provide a temperature corrected output voltage in response to said raw output voltage and said voltage offset.

A method for logarithmically amplifying a voltage input signal comprising the steps of:

• receiving a voltage input signal having an amplitude;
• providing a first rectified voltage signal in response to said voltage input signal;
• providing a second rectified voltage signal responsive to said first rectified voltage signal;
• combining said first and second rectified voltage signals to provide a signal strength indicator voltage having an amplitude such that said input voltage amplitude has a geometric relation to said signal strength indicator voltage amplitude;
• providing a voltage offset responsive to temperature;
• and
• providing a temperature corrected signal strength indicator voltage in response to said voltage offset and said signal strength indicator voltage.