Differential integrator and related circuitry

A multi-node common-mode feedback circuit comprising:

• common-mode feedback circuitry for determining a difference between an input voltage and a reference voltage and for adjusting at least one current branch based on the difference;
• and
• at least one current source, coupled to the common-mode feedback circuitry, for receiving at least one current signal via the at least one current branch;
• wherein a first current branch and a second current branch are adjusted simultaneously to compensate for common-mode correction.

A nap mode circuit comprising:

• logic circuitry for receiving a nap signal and a feedback signal and for determining a sleep mode based thereon;
• and
• storage circuitry, coupled to the logic circuitry, for storing a differential charge by disconnecting a differential path during the sleep mode;
• wherein a differential voltage is held constant prior to a wake-up mode to shorten a wake-up time.

A level shifter circuit for level shifting differential signals comprising:

• first charge storage circuitry for receiving differential signals at an input node;
• charge pump circuitry, coupled to the first charge storage circuitry, for level shifting the differential signals and for generating level shifted differential signals;
• second charge storage circuitry, coupled to the charge pump circuitry, for storing the level shifted differential signals and for generating output signals to an output node based thereon;
• and
• at least one pair of switches coupled to the charge pump circuitry for enabling charge to flow between the input node and the output node so as to establish an equilibrium therebetween.

A method for reducing offset in a desired common-mode of an output signal of a differential integrator, the method comprising the steps of:

• receiving an input signal having a bandwidth;
• generating an output signal based upon the input signal, the output signal being generated slower than the bandwidth of the input signal but faster than a lock time of the differential integrator;
• comparing the output signal and a reference voltage;
• generating at least one bias signal based at least in part upon the comparison;
• and
• reducing offset in a desired common-mode of the output signal based at least in part upon the at least one bias signal.

A method for generating a time-average gain boosted differential voltage in an integrating gain boosted cascode circuit, the method comprising the steps of:

• receiving substantially equal input voltages;
• generating a differential voltage, based upon the input voltages, to compensate for channel length modulation;
• and
• generating an output slew rate of the differential voltage which is slower than an input slew rate of the input voltages such that the differential voltage is a time-averaged gain boosted differential voltage.

A method for compensating for common-mode correction in a multi-node common-mode feedback circuit, the method comprising the steps of:

• determining a difference between an input voltage and a reference voltage;
• adjusting at least one current branch based on the difference;
• and
• receiving at least one current signal via the at least one current branch, wherein a first current branch and a second current branch are adjusted simultaneously to compensate for common-mode correction.

A method for implementing a nap circuit, the method comprising the steps of:

• receiving a nap signal and a feedback signal;
• determining a sleep mode based upon the nap signal and the feedback signal;
• and
• storing a differential charge by disconnecting a differential path during the sleep mode, wherein a differential voltage is held constant prior to a wake-up mode to shorten a wake-up time.

A method for level shifting differential signals, the method comprising the steps of:

• receiving differential signals at an input node;
• level shifting the differential signals;
• storing the level shifted differential signals;
• generating output signals to an output node based upon the stored level shifted differential signals;
• and
• enabling charge to flow between the input node and the output node so as to establish an equilibrium therebetween.